Hewlett-packard Development Company, L.p.

Intel Corporation

Hewlett-packard Company

Sk Hynix Nand Product Solutions Corp.

Karl P Brummel

Keith D Underwood

Kevin Safford

Russell C Brockmann

Charles A Giefer

Patrick Knebel

Nathan S Miller

Jeremy Petsinger

Bruce M Pirie

Bruce A Long

Donald Charles Soltis, Jr

Bradley A Burres

Rohit Bhatia

Jose Niell

Mark Debbage

Shawn Kenneth Walker

J Michael Hill

Todd W Mellinger

Eric R Borch

Stephanie L Hirnak

John Greth

Kiel Boyle

David Addison

M A Susith Rohana Fernando

Keith Shaw

David Noeldner

Examples described herein relate to migrating a virtualized execution environment from a first platform to a second platform while retaining use of namespace identifiers and permitting issuance of storage transactions by the virtualized execution environment. The first platform can include a first central processing unit or a first network interface. The second platform can include a central processing unit that is different that the first central processing unit and a network interface that is the same or different than the first network interface. The second platform can retain access permissions and target media format independent of one or more identifiers associated with the migrated virtualized execution environment at the second platform. Unperformed storage transactions can be migrated to the second platform for execution.

Maintaining storage namespace identifiers for live virtualized execution environment migration

Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

Methods and arrangements to accelerate array searches

A computing device, a method, and a system to enforce concurrency limits within a network fabric. The computing device includes a memory device; and a network interface controller coupled to the memory device. The network interface controller includes circuitry to communicate with a plurality of target computing devices in a network fabric. The circuitry is configured to generate packets for transmission to respective ones of a plurality of target nodes. For each packet addressed to its corresponding target node, the circuitry is to determine whether transmitting the packet would violate the target node's concurrency limit. If transmitting the packet would not violate the target node's concurrency limit, the circuitry is to transmit the packet to the target node. However, if transmitting the packet would violate the target node's concurrency limit, the circuitry would store the packet in a retransmit buffer of the computing device, where the retransmit buffer is to further store already transmitted packets flagged for retransmission. The circuitry would then transmit the packet from the retransmit buffer when transmitting the packet from the retransmit buffer would not violate the target node's concurrency limit.

Device, method and system to enforce concurrency limits of a target node within a network fabric

Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.

Congestion management techniques for communication networks

Technologies for tracking out-of-order network packets include a target computing node coupled to a source computing node via a communication channel. The target computing node is configured to allocate a small window in memory in which to store a bit mask corresponding to a number of out-of-order network packets received from the source computing node via the communication channel. The target computing node is further configured to update the bit mask in the small window upon receiving an out-of-order network packet from the source computing node. The target computing node is additionally configured to allocate a large window in memory in response to a determination the size of the bit mask is larger than the size of the small window, store the bit mask in the large window, and store a pointer to the large window in the small window. Other embodiments are described and claimed.

Technologies for tracking out-of-order network packets

In an embodiment, an out-of-order, reliable, end-to-end protocol is provided that can enable direct user-level data placement and atomic operations between nodes of a multi-node network. The protocol may be optimized for low-loss environments such as High Performance Computing (HPC) applications, and may enable loss detection and de-duplication of packets through the use of a robust window state manager at a target node. A multi-node network implementing the protocol may have increased system reliability, packet throughput, and increased tolerance for adaptively routed traffic, while still allowing atomic operations to be idempotently applied directly to a user memory location.

Reliable out-of order end-to-end protocol with robust window state overflow management and a multi-node system using same

A cache memory system capable of adaptively accommodating various memory line sizes comprises cache memory and cache logic. The cache memory has sets of ways. The cache logic is configured to request a memory line in response to a cache miss, and the memory line represents a portion of a way line. The cache logic is configured to select one of the ways based on which portion of the way line is represented by the memory line. The cache logic is further configured to store the memory line in the selected way.

Cache memory system and method capable of adaptively accommodating various memory line sizes

The present invention relates to an improved microprocessor having a memory system with several caches that can be operated to provide virtual memory. Among the caches included in the microprocessor are conventional caches that store data and instructions to be utilized by the processes being performed by the microprocessor, and that are typically arranged in a cache hierarchy, as well as one or more translation lookaside buffer (TLB) caches that store a limited number of virtual page translations. The improved microprocessor also has an additional cache that serves to store a virtual hash page table (VHPT) that is accessed when TLB misses occur. The introduction of this VHPT cache eliminates or at least reduces the need for the microprocessor to look for information within the caches of the cache hierarchy or in other memory (e.g., main memory) outside of the microprocessor when TLB misses occur, and consequently enhances microprocessor speed.

System and method for responding to TLB misses

A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, comprises the steps of: writing test data words in parallel to the rows of the plurality of memory blocks; reading out test data words in parallel from the rows of the plurality of memory blocks to a corresponding plurality of on-chip data word comparators; presenting corresponding expected data words in parallel to the plurality of on-chip data word comparators for comparison with the read out data words of the corresponding memory blocks; concurrently comparing corresponding data bits of the read out data words and expected data words in corresponding data bit comparators to generate a column status bit for each data bit comparison; latching the column status bit of a mismatch bit comparison in the corresponding data word comparator; and reading the column status bits of each on-chip data word comparator.

System and method of testing a plurality of memory blocks of an integrated circuit in parallel

An apparatus verifies the correctness of a behavioral model of a microcode machine, where the microcode machine is operable in a native state and an emulated state. The apparatus includes means for producing the native state, means for producing the emulated state, and means for comparing the native state and the emulated state. Corresponding to the apparatus, a method verifies the correctness of a processor behavioral model, where the processor operates in a native mode state and an emulated mode state. The method includes determining if a macroinstruction to be executed is a native instruction, and, if the macroinstruction is a native instruction, executing the native instruction, the execution producing the native mode state of the processor. The method further includes, if the macroinstruction is not a native instruction, fetching the macroinstruction, providing microinstructions corresponding to the macroinstruction, and executing the microinstructions, the execution producing the native mode state of the processor. Finally, the method includes executing the macroinstruction, the execution producing an emulated state of the processor, and comparing the native mode state the of the processor with the emulated state of the processor.

Method and apparatus for verifying the correctness of a processor behavioral model

A method and apparatus produce random computer code for testing integrated circuit. The method begins by generating a random weight for an instruction type, and then generating randomly determined computer code. A statistical likelihood of generating the instruction type in the code is based on the random weight for the generated instruction type. The apparatus includes a random value generator that generates a random weight and a random code generator that is connected to the random value generator. The random code generator produces an output file in which the proportion of at least one computer instruction type is related to the random weight produced by the random value generator.

Method and apparatus for generating random code

An apparatus and a method of testing computer microarchitectures has a test writer create a test sequence written directly in microinstructions (both native-mode and emulation-only microinstructions). The microinstruction sequence is then inserted into a reprogrammable microcode storage, replacing the normal sequence of microinstructions for a given macroinstruction. In order to execute the microinstructions, the test writer can issue the macroinstruction. The method may be implemented in a simulation model where one set of microinstructions in the reprogrammable microcode storage can be easily replaced. The method may also be applied to an actual microprocessor implementation.

Method and apparatus for testing microarchitectural features by using tests written in microcode

A method and an apparatus checks the fine-grain correctness of a microcode machine central processor unit (CPU) behavioral model. Macroinstructions are decomposed into microinstructions and each microinstruction is executed sequentially. A sequence of microinstructions is determined by an emulated microinstruction sequencer, using dynamic execution information, including information from execution of prior microinstructions in the sequence of microinstructions. At the end of execution of each microinstruction, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted. After execution of all microinstructions in the microinstruction sequence, a reference state is compared to a corresponding state of the behavioral model, and any differences are noted.

Method and apparatus for verifying the fine-grained correctness of a behavioral model of a central processor unit

The present invention provides a method and apparatus for testing architectural compliance of processors wherein various types of cases requiring some structure can be simulated and a degree of randomness can be added to the case without destroying the structure of the case. The apparatus comprises a computer capable of being configured to execute a testing program. When the computer is executing the testing program, the computer generates instructions and simulates execution of the instructions in a processor. During simulation, the computer detects when simulation of an instruction has caused an event to occur in the processor. The computer identifies the event that has occurred and generates a list of atoms and stores the list in a memory device in communication with the computer. Each of the atoms in the list corresponds to a description of a particular event handler task to be performed by the processor in response to the occurrence of the event. The atoms are then read out of the list and instructions corresponding to the atoms are generated and simulated to handle the event. The sequence in which these instructions are simulated can be randomized by either inserting the atoms into the list with a degree of randomness or by reading the atoms out of the list with a degree of randomness. The degree of randomness is added to the case without destroying the structure of the case.

Method and apparatus for evaluating processors for architectural compliance

During generation of a test case, in response to a predictable interrupt condition a dynamic portion of a dynamic trap handler is created. The static portion of the dynamic trap handler is generic trap handler code that is not dynamically created and performs such routine tasks as loading the trap number of the interrupt condition, loading a trap code pointer and preparing the processor to branch to the location pointed to by the trap code pointer. The dynamic portion of the trap handler, however, is dynamically created in response to each interrupt condition which occurs. The unique series of instructions of the dynamic portion of the trap handler may be tailored as desired to perform any number of tasks, including verifying the trap handler, verifying trap parameters, generating code to return to a new location upon completion of the trap handler, fixing the interrupt condition, updating the trap vector table, and updating the trap code pointer and a trap data pointer. Any number of other tasks may also be added to the dynamic portion of the trap handler.

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Chicago, IL, United States of America

Karl P Brummel