Infineon Technologies Austria Ag

Infineon Technologies Ag

Karl Norling

Erwin Huber

Dieter Draxelmayr

Simone Fabbro

Bernhard Wicht

Johannes Groeger

Anton Mauder

Gerald Deboy

Sergio Morini

Uwe Kirchner

Adriano Sambucco

Harald Christian Koffler

Martina Arosio

Benjamim Tang

Giuseppe Bernacchia

Christian Lindholm

Jens A Ejury

Wolfgang Frank

Fabio Padovan

Aliaksandr Subotski

Matteo Bassi

David Grant Cox

Saleh Karman

Alexander Schreiber

Nathalie Abry

Natasa Pojak

Johannes Gröger

A device includes: first and second electronic sides; an isolation barrier galvanically isolating the electronic sides from one another and including a signal coupler configured to enable signaling between the electronic sides over the isolation barrier via electromagnetic coupling; and transceiver circuitry included in both electronic sides and configured to implement, based on a frequency response profile of the isolation barrier, full-duplex communication between the electronic sides using the same signal coupler. According to another embodiment of a device, the device includes: electronic circuitry; an isolation barrier galvanically isolating the electronic circuitry and including a signal coupler configured to enable signaling over the isolation barrier via electromagnetic coupling; and transceiver circuitry configured to implement, based on a frequency response profile of the isolation barrier, full-duplex communication between the electronic circuitry of the device and electronic circuitry of another device using the same signal coupler.

Devices, systems and methods for multiple channel communication across an isolation barrier

A method for protecting a power switch during turn-on includes sensing that a change in current through the power switch is in regulation, measuring a time the change in current through the power switch is in regulation, and comparing the time the change in current through the power switch is in regulation to a reference time. An over current signal, which can be used to disable the power switch, is generated if the time the change in current through the power switch is in excess of the reference time.

Method of over current and over voltage protection of a power switch in combination with regulated DI/DT and DV/DT

A system and method for an overcurrent detector includes a device. The device includes a threshold generation circuit, and an overpower determination circuit. The threshold generation circuit is configured to produce a threshold value based on an output of a temperature sensor proximate to a power transistor, and a maximum power dissipation in the power transistor. The overpower determination circuit is configured to determine an overpower state of the power transistor based on the threshold value and a switch voltage. The switch voltage is detected between a source and a drain or a collector and an emitter of the power transistor.

System and method for an overpower detector

A gate driver circuit includes a gate driver and a sensing circuit. The gate driver is configured to generate an on-current during a plurality of turn-on switching events to drive a transistor, where a voltage across the transistor changes from a first value to a second value with a slope during the plurality of turn-on switching events, where the slope is of either an active type dependent on an amplitude of the on-current or a passive type. The sensing circuit determines whether the slope during a first turn-on switching event is the active type or the passive type, and regulates the amplitude of the on-current during a second turn-on switching event that is subsequent to the first turn-on switching event if the slope is the active type and to maintain the amplitude of the on-current as unchanged during the second turn-on switching event if the slope is the passive type.

DV/DT self-adjustment gate driver architecture

An electronic circuit includes an electronic switch having a control terminal and a load path and also includes a monitoring circuit comprising a switched-capacitor circuit with at least one capacitive storage element. The switched-capacitor circuit coupled to the load path of the electronic switch. The circuit can be operated by using the monitoring circuit to evaluate a load voltage of the electronic switch and to generate a failure signal dependent on the evaluation and providing a drive signal at the control terminal of the electronic switch dependent on the failure signal.

Method of operating an electronic circuit with an electronic switch

A multi-output gate driver system comprises a power device having a gate node; a first driver having an input and an output coupled to the gate node; a second driver having an input and an output coupled to the gate node; a first comparator having a first input coupled to the output of the second driver, a second input coupled to a first reference voltage, and an output; a second comparator having a first input coupled to the output of the second driver, a second input coupled to a second reference voltage, and an output; and a logic circuit having an input for receiving a control signal, a first output coupled to the input of the first driver, and a second output coupled to the input of the second driver.

Method for static gate clamping in multi-output gate driver systems

A system includes a control circuit having first and second detectors coupled to a first node of the control circuit, first and second filters coupled to the first and second detectors, and a logic circuit coupled to the first and second filters, a diode circuit having a first node coupled to the first node of the control circuit, and a switch having a first current node coupled to a second node of the diode circuit, a gate coupled to a second node of the control circuit, and a second current node coupled to a third node of the control circuit, wherein a first detector is used to provide a first event overcurrent signal and a second detector is used to provide a multiple event overcurrent signal or a warning signal.

Configurable integrated desaturation filter

A method for protecting a power switch during turn-on includes sensing that a change in current through the power switch is in regulation, measuring a time that the change in current through the power switch is in regulation, and comparing the time that the change in current through the power switch is in regulation to a reference time. An over current signal, which can be used to disable the power switch, is generated if the time that the change in current through the power switch is in excess of the reference time.

In accordance with an embodiment of the present invention, a circuit includes a configurable clamp driver circuit for clamping a voltage at a gate terminal of a transistor below a turn-on voltage threshold upon switch-off of the transistor. In a first clamp driver circuit mode, an output terminal of the clamp driver circuit is configured to be coupled to the gate terminal of the transistor to provide a first discharge path from the gate terminal of the transistor upon switch-off of the transistor. In a second clamp driver circuit mode, the output terminal of the clamp driver circuit is configured to be coupled to an input terminal of a clamp circuit, wherein the clamp circuit is coupled to the gate terminal of the transistor to provide a second discharge path from the gate terminal of the transistor upon switch-off of the transistor.

Configurable clamp circuit

In accordance with an embodiment, a method of driving a switching transistor includes driving the switching transistor with a gate drive signal; measuring at least one of a derivative of a load path voltage and a derivative of a load path current of the switching transistor; measuring a derivative of the gate drive signal; forming an error signal based on a reference signal, a measured derivative of the gate drive signal, and at least one of the measured derivative of the load path voltage of the switching transistor or the measured derivative of the load path current of the switching transistor; and forming the gate drive signal, where forming the gate drive signal includes processing the error signal using a dynamic controller.

System and method of driving a power switch in combination with regulated DI/DT and/or DV/DT

A method for operating a gate driver circuit includes supplying power to the gate driver circuit from a power supply including a positive power supply voltage and a negative power supply voltage. The method also includes comparing the negative power supply voltage with a first voltage at an output terminal of a transistor, wherein the gate driver circuit is coupled to a gate terminal of the transistor. The method also includes operating the gate driver circuit when the negative power supply voltage is more negative than a trigger voltage, wherein the trigger voltage is a predetermined voltage above the first voltage. The method also includes deactivating at least a portion of the gate driver circuit when the negative power supply voltage is more positive than the trigger voltage.

System and method for circuit protection

In accordance with an embodiment, a method of driving a switching transistor includes receiving an activation signal for the switching transistor and generating a sequence of random values. Upon receipt of the activation signal, a control node of the switching transistor is driven with a drive strength based on a random value of the sequence of random values.

System and method for a switch transistor driver

An embodiment bus device with a programmable address includes a bus communication circuit connected to a bus terminal, a first pin terminal, a memory having a first register with a first address stored therein and a second register, and a state logic circuit. The state logic circuit detects a chip select signal on the first pin terminal, receives a first message through the bus communication circuit while the chip select signal is asserted, determines that the first message indicates an address set command, and saves an address value in the first message as a second address in the second register in response to a target address in the first message matching the first address. The state logic circuit further processes a second message received through the bus communication circuit in response to a target address of the second message matching the second address.

Growing community of inventors

Villach, Austria

Karl Norling