Western Digital Corporation

Sandisk Corporation

Sundisk Corporation

Karl M Lofgren

Gerald W Shearer

Robert D Norman

Anil K Gupta

Kenneth W Ouyang

Jeffrey Donald Stai

Sanjay Mehrotra

John S Mangan

Jeffrey G Craig

Ronald E Wilson

Richard Albert

Gregory B Thelin

Charles W Frank, Jr

A memory system includes an array of solid-state memory devices are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is assigned an array address by an array mount. An memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array mount configuration is used to unconditionally select the device mounted. A reserved address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

Device and method for controlling solid-state memory system

A mass storage system made of flash electrically erasable and programmable read only memory ('EEPROM') cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

Wear leveling techniques for flash EEPROM systems

A memory system includes an array of solid-state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it. A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A particular multi-bit mount configuration is used to unconditionally select the device mounted thereon. A predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

A file structure employed in a flash electrically erasable and programmable read only memory ('EEPROM') system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.

Flash EEPROM array data and header file structure

A memory system includes an array of solid-state memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit and assigned an array address. A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A particular multi-bit mount configuration is used to unconditionally select the device mounted thereon. A predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.

Solid state memory system including plural memory chips and a serialized

A phase-locked system for recovering data from a disk drive includes a phase detector for signalling the difference in phase between incoming delayed data pulses and a phase detection window clock signal. The phase detection window clock signal is derived from one output of an integrated-circuit window generator, driven by the output of a voltage-controlled oscillator whose frequency is controlled by the phase detector. The phase-locked loop is completed by comparing the phase detection window clock signal output of the window generator with the incoming delayed data pulses in the phase detector. Data detection window clock pulses, defining time windows in which the delayed data pulses are exactly centered, are produced at a second output of the window generator which has a line about which it is essentially symmetric, resulting in the two outputs of the window generator being exactly 180.degree. apart in phase from each other.

Data synchronizer with symmetric window generation

A phase locked loop system having a non-linear voltage controlled oscillator (VCO) is provided with a variable gain charge pump. The charge pump supplies a pump current to an integrating network which transforms the pump current into a frequency-modulating input voltage. The frequency-modulating input voltage is applied to an input of the VCO. The frequency-modulating input voltage is also coupled to a gain control input of the variable gain charge pump so that the magnitude of the pump current will be a function of the absolute value of the frequency-modulating voltage. A substantially constant loop gain may be obtained in the phase locked loop system by arranging the gain function of the variable gain charge pump in counterposed relation to the slope of a VCO transfer function defining the nonlinear relation between the frequency-modulating input voltage of the VCO and the output frequency of the VCO.

Variable frequency system having linear combination of charge pump and

A circuit for providing precise delays includes a phase-locked loop driven by a reference frequency source such as a crystal oscillator and including a variable delay circuit. The output of the oscillator is applied to the delay circuit and the non-delayed and delayed signals are compared in a phase comparator. An error signal representative of phase error is developed and applied to vary the amount of delay until the phase error is eliminated. A precise delay referenced to the oscillator frequency is therefore achieved.

Phase-locked loop delay line

An integrated circuit chip is fabricated with an operational active device and a nearly-identical, exemplary active device. The exemplary device is connected in series with a current reference element so that current flow through the reference element will be substantially duplicated in the exemplary device. A difference amplifier senses the output voltage of the exemplary device; compares it to a provided reference voltage; and generates a gate biasing level at the gate of the exemplary device to force the output voltage of the exemplary device substantially equal to the reference voltage. The biasing level at the gate of the exemplary device is duplicated at the gate of the operational device thereby creating a condition wherein the output current of the operational device will be a substantially precise replica of the current flow through the reference element when the reference voltage is duplicated across the output of the operational device.

Biasing circuit for generating precise currents in an integrated circuit

An integrated system for use in a disk drive system for the implementation of write precompensation for recording of data and read window margining for accelerated testing of the disk drive. Both functions are provided by a common delay-line circuitry. The output of the delay line circuit is applied to both window shifting and write precompensation. An on-board read detection error analysis can be performed after installation of the drive in a computer system in its final configuration. Actual read error tolerance based on the overall system in its actual operating condition can thus be obtained. Enhanced data recovery techniques are also facilitated.

Integrated system for implementation of read window margining and write

A flip-flop circuit is provided for use in a phase-locked loop circuit, the flip-flop having two signal paths for selecting a VCO output during velocity lock and phase lock. The two signal paths comprise identical environments and therefore eliminate the phase step exhibited by prior art designs in shifting between velocity lock and phase lock. The circuit is also useful in any application where a clock to output delay of a flip-flop connected for normal operation, must have its propagation delay matched to a circuit which simply delays a signal by the same amount.

Flip-flop with identical propagation delay in clock pass through mode

A voltage controlled oscillator includes an inverting amplifier connected to a resonant feedback network and a comparator for comparing the input to the inverting amplifier to a reference voltage which is equal to the threshold voltage of the inverting amplifier. As a result, the oscillator provides a square wave output having a precise one-to-one duty cycle. In addition, circuitry is included for causing the oscillator to start up at a steady state value and predetermined phase.

Precise phase start-up voltage controlled oscillator with accurate duty

The present invention provides a circuit which facilitates fast and reliable start-up of an oscillator crystal without the amplification of undesirable frequencies of noise. A crystal is provided which is connected in parallel to an amplifying inverter having an input and an output. Grounded capacitors are connected respectively to the input and output of the inverter for stability. A first high resistance feedback path and a second low resistance feedback path are provided between the output of the inverter and the input of the inverter. A switch is also provided for selectively engaging or disengaging the low resistance feedback path with the inverter at preselected points in time. During operation of the circuit in the preferred manner, the switch engages the low resistance feedback path with the inverter to allow maximum charge build-up at the stabilizing capacitors upon turn-on of a supply voltage, thus quickly generating a large input voltage at the inverter. The voltage at the input of the inverter quickly becomes equal to the voltage at the output of the inverter, resulting in high gain. Thereafter, the switch disengages the low resistance path from the inverter, creating a voltage transition. The voltage transition results in high level noise which may quickly be amplified by the high gain inverter to generate maximum amplitude at the crystal. The high resistance path keeps the inverter biased at high gain, while the opening of the low resistance path minimizes noise during subsequent oscillator operation.

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Newport Beach, CA, United States of America

Karl M Lofgren