Theseus Research, Inc.

Theseus Logic Inc.

Honeywell G.m.b.h.

Wave Semiconductor, Inc.

Other

Princeton Video Image, Inc.

Theeus Logic

Karl M Fant

Scott A Brandt

Gerald Edward Sobelman

David A Parker

Larry L Kinney

Carl P Graf

Werner H Egli

John Edward Overland

Patrenahalli M Narendra

Michael O Schroeder

Bindinganavle R Suresh

Darrell S DiCicco

George W Rusler

Kim M Fairchild

Scott E Johnston

David A Duncan

Larry Kinney

Richard A Fundakowski

Tod S Levitt

Karen S Rylander

Franz W Ulrich

Systems and methods for clock generation and distribution are disclosed. Embodiments include arrangements of synchronization signals implemented using a mesh circuit. The mesh circuit is comprised of a plurality of null convention logic (NCL) gates organized into rings. Each ring shares at least one NCL gate with an adjacent ring. The rings are configured in such a way that each ring in the mesh operates synchronously with the other rings in the mesh.

Hum generation circuitry

Invocation language is described that is suitable for controlling a machine to perform a process having concurrent parts. Each concurrent part has an association relationship, a completeness relation, and an invocation expression.

Systems and methods using an invocation model of process expression

An electronic processing element is disclosed for use in a system having a plurality of processing elements. The electronic processing element includes an input instruction memory, an operation unit, and an output instruction memory. The input instruction memory is configured to store and retrieve a plurality of operation codes and, for each operation code, an associated output instruction memory address. The operation unit is configured to generate an output datum defined by at least a selected operation code and an associated input datum. The output instruction memory is configured to receive the output instruction memory address and to retrieve an address for an input instruction memory of a second processing element. Upon selection of an input instruction memory address and presentation of an associated input datum, the processing element generates an output datum in association with a corresponding input instruction memory address of the second processing element.

Concurrent processing element system, and method

A programming language for representing processes as strings of symbols has a syntax delimiting places in a symbol string. A convention associates delimited places in symbol strings. An invocation construct instantiated as an invocation string. A definition construct instantiated as a definition. Completeness of input of the invocation destination list is sufficient for resolving the process defined by a definition string.

Method and language for process expression

An array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data.

Programmable pipeline array

Disclosed is an array of programmable data-processing cells configured as a plurality of cross-connected pipelines. An apparatus includes cells capable of performing data-processing functions selectable by a presented instruction. A first set of cells includes an input cell, an output cell, and a series of at least one interior cell providing an acyclic data processing path from the input cell to the output cell. Additional cells are similarly configured. Memory presents configuration instructions to cells in response to a configuration code. Data advances through ranks of the cells. The configuration code advances to memory associated with a rank in tandem with the data.

A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Null convention threshold gate

A switching element and method for asynchronous logic switches an output signal according to a switching-logic relationship between or among input signals. Input signals may assume at least a DATA value, a NULL value, and an INTERMEDIATE value. Input signals may also assume multiple DATA values. The element and method generates an output which assumes a NULL value when all input signals are NULL, and assumes DATA and INTERMEDIATE values in accordance with transform rules. Output signals may also assume an INTERMEDIATE value. DATA, NULL and INTERMEDIATE values may be encoded on to a number of signal lines. Transform rules may be threshold switching rules, where the output switches to a DATA output when a number of DATA inputs is greater than a threshold.

Asynchronous logic with intermediate value between data and null values

An invocation architecture for generally concurrent process resolution comprises a plurality of interconnected processors, some of the processors being homogeneous processors and others of the processors being special purpose processors. Each homogeneous processor being capable of invoking a connected processor to have the connected processor resolve instructions. Each processor capable of being invoked by a connected processor to resolve instructions at the invocation of the connected processor.

Invocation architecture for generally concurrent process resolution

A NULL convention asynchronous register regulates wavefronts of signals through a NULL convention sequential circuit. The asynchronous register receives a control signal from a downstream circuit when the downstream circuit is ready to receive a new wavefront. Wavefronts alternate between meaningful data and NULL. The asynchronous register further generates a feedback signal to upstream circuits so that upstream circuits generate a wavefront when the sequential circuit is ready to receive the wavefront. Asynchronous registers can be used to create a variety of architectures, and to store data, as in a sequential circuit (state machine).

Asynchronous register

An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line based upon an evaluation of at least one data input value and an acknowledgment collection circuit, embedded in the data threshold circuit, for collecting a plurality of acknowledge signals and resolving the acknowledge signals for controlling, in combination with the at least one data input value, the passing of the data or NULL values to the output signal line. The acknowledgment collection circuit includes an M of N acknowledge collection circuit, wherein N is an integer representing the number of acknowledge signals being resolved and M representing a threshold, wherein M.ltoreq.N. The M of N acknowledge collection circuit allows the data input values to pass as data to the output signal line after M acknowledge signals assert a request for data and allows the data input values to pass as NULL to the output signal line after P acknowledge signals assert a request for NULL, wherein P.ltoreq.N. P may or may not be equal to M. A reset network is provided for providing system initialization at registration boundaries and is made transparent during normal operating conditions.

Asynchronous registers with embedded acknowledge collection

A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which is programmed to function as a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume a DATA state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of DATA inputs exceeds the threshold value. The gate preferably exhibit hysteresis such that the output remains DATA while the number of DATA inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, and array of simplified threshold elements is used to form more complex threshold gates.

Look up table threshold gates

A threshold gate with registration embedded in the threshold logic is disclosed. A go-to-NULL network and a go to-data network receives data input having an asserted state and a NULL state. A directive or acknowledge signal is received by the embedded registrations network. The directive signal indicates whether an asserted state or the NULL state is desired at the output signal line. A data processing network is coupled to the go-to-NULL network to provide an output signal based upon the go-to-NULL network, the go-to-data network and the registration network. The go-to-data network provides a network of switches that cause an asserted state at the output signal line when a number of the data inputs in the asserted state exceeds a predetermined threshold and the acknowledge signal is in the asserted state. The go-to-NULL network provides a network of switches that cause a NULL state at the output signal line when all of the data inputs are in the NULL state and the acknowledge signal is in the NULL state. A reset network is included for providing system initialization at registration boundaries. The reset network is made transparent during normal operating conditions.

Dynamic threshold gates with embedded registration

An electronic data processing circuit is disclosed having at least an instruction memory, an instruction decoder; and a slot structure. The slot structure is characterized by a plurality of slots. Each slot has at least: (1) an address register (2) a data register, (4) a function register, and (3) a monitoring circuit. Each slot asynchronously performs operations defined by the information content of their respective address register, data register and function register when complete information is present.

Growing community of inventors

Minneapolis, MN, United States of America

Karl M Fant