Arm Limited

International Technological University

Iot Technology Corporation

Karl Lin Wang

Hemangi Umakant Gajjewar

Moon-Hae Son

Ingming Chang

A biometric classification system includes a biometric capture system that captures a biometric identifier. A classifier includes a plurality of group classifiers. Each group classifier in the plurality of classifiers includes a group discriminator that determines, based on the captured biometric identifier, whether the biometric identifier belongs to a group of persons associated with the group discriminator, and includes a plurality of object discriminators. Each object discriminator is associated with a single person within the group of persons. The group discriminator determines whether the biometric identifier belongs to the group of persons. The object discriminator determines whether the biometric identifier belongs to the single person associated with the object discriminator.

Classification system

An improved data packet design that can be used in a variety of data communication standards used in smart meter systems is disclosed. In an embodiment a smart meter system that comprises of a local server, a coordinator and a plurality of smart meters in the many-to-one data communication system configuration. The smart meter uses a variety of types of radio frequency data packets. The data packets contain the commands, parameters, and data for system control and data transmission. The data packet designs are disclosed for a route discovery command, a get parameter command, a set parameter command, a get data command, a reset command, a relay command, a start command, and a calibration command that are used in the smart meter system.

Smart meter system communication methods

A smart meter system architecture comprises of a local server, a coordinator, and a plurality of smart meters in a one-to-many data communication system configuration is disclosed. The invention discloses the architecture for a coordinator-server interface control register, data registers, routing table, non-volatile memory, parameter register, non-interruptible battery backup subsystem, and a low-power energy calculation and calibration method for resistive loads.

Smart meter system architecture

A transformer-less method and system for voltage and current sensing using voltage drops across resistors is disclosed. Using optically coupled isolators, the sensed voltages in the high voltage power lines are optically coupled and electrically isolated to the low voltage circuits. The circuit designs for voltage and current sensing's and electrical isolation are disclosed.

Smart meter voltage sensing using optically coupled isolators

Smart meter voltage and current sensing using optically coupled isolators

An integrated circuit memory includes multiple memory banks grouped into repair groups Group, Group. One memory has redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

Redundancy architecture for an integrated circuit memory

An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group, Group. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of the memory banks within the common repair group concerned. Redundant columns of memory cells are also provided and these may be substituted for defective columns by multiplexing circuitry. This multiplexing circuitry shifts the bit lines which are selected to form part of a bit group to access a given data bit by an amount less than the multiplexing width being supported by that multiplexing circuitry thereby reducing the number of redundant columns which need be provided.

A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged as two cross coupled inverters. It is converted to a read only memory cell by severing a connection between at least one of said transistors within a first of said two inverters and one of said voltage supply lines such that when powered said first inverter outputs a predetermined value.

Converting SRAM cells to ROM cells

A memory cell includes polysilicon gatesrunning in a first direction. A sequence of layers metal lines includes a layer of bit linesrunning in a second direction substantially orthogonal to the first direction followed by data linesrunning in that second direction and then word linesrunning in the first direction. The data linesare precharged to a value which is held whilst the bit linesare being used to sense data values stored within a memory cell.

Metal line layout in a memory cell

An integrated circuit memory includes memory cellsis connected to a power supply Vdd via a power supply control circuit. The power supply control circuit includes a first gateand a second gate. The first gateis switched by a write assist circuit so as to be non-conductive when writing to the memory cell. The second gateis conductive both when writing to the memory celland when not writing to the memory cell. Accordingly, when a write operation is made a relatively high resistance path is formed through the power supply control circuitcompared to when writing is not being performed. This increase in the resistance through the power supply control circuitduring write operations induces a dip in the virtual supply voltage provided at the supply output of the power supply control circuitin a manner which assist writes to be made. If individual memory cellstend to resist changes in their state more strongly, then they will tend to draw more current which will in turn result in a larger virtual supply voltage dip which will assist more strongly in encouraging those memory cellsto change state.

Integrated circuit memory with write assist

A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected to its inputs, and is arranged to connect one of those inputs to its output dependent on a multiplexer control signal. Decoder logic is responsive to an address to produce the multiplexer control signal and to select one of the word lines, as a result of which a particular memory cell in the memory array identified by the address has its associated bit line connected to the output of a multiplexer logic. Sense amp logic is coupled to the output of the multiplexer logic and has a precharge node used during a sensing operation to detect a stored data state of the particular memory cell. Control logic initiates the sensing operation and causes the precharge node of the sense amp and at least the bit line associated with the particular memory cell to be precharged in a precharge operation prior to the sensing operation. Further, isolation logic is provided between the output of the multiplexer logic and the precharge node of the sense amp logic to isolate the precharge node from the capacitance of the output of the multiplexer logic during the sensing operation.

Growing community of inventors

Los Altos, CA, United States of America

Karl Lin Wang