Motorola Corporation

Karl L Wang

Mark D Bader

Ray Chang

Kenneth W Jones

Jin-Uk 'Luke' Shin

Bich-Yen Nguyen

Wei E Wu

Ruey J Yu

Lal C Sood

Taisheng Feng

Ker-Wen Teng

Pei-chun P Liu

Peter H Voss

A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1.times. and 2.times. architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

Digital signal processor having an on-chip pipelined EEPROM data memory

A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1X and 2X architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

Pipelined fast-access floating gate memory architecture and method of

A content addressable memory system has a plurality of associated circuit sets (12). Each circuit set has a tag memory element, a latching circuit and a data memory element. Each tag memory element stores a received tag in a first mode of operation and compares a received data tag to a stored data tag in a second mode of operation. In the second mode of operation, the tag memory element couples a first voltage supply terminal to an associated node in response to the comparison. Each latching circuit latches the voltage level present on its associated node during a first phase of a control signal. Each data memory element stores a data word and outputs the data word responsive to the latched voltage level of the associated latching circuit. The latching circuit continues to latch the voltage level and the data memory element continues to output its data word for an entire clock cycle. Each latching circuit couples its associated node to a second voltage supply terminal during a first phase of the control signal.

Content addressable memory system and method of operation

A modified Widlar current source (74) includes a first transistor (84) having a collector providing a first terminal of the current source (74), a base, and an emitter connected through a first resistor (85) to a second terminal of the current source (74). A second transistor (82) has a collector connected to a power supply voltage terminal through a second resistor (81) and to the base of the first transistor (84), a base connected to the collector thereof, and an emitter connected to the second terminal of the current source (74) through a third resistor (83). A switching portion (80) selectively reduces a resistance between the power supply voltage terminal and the collector of the second transistor (82) in response to a control signal. Thus, current is selectively reduced, such as during a non-switching time of a logic circuit (70).

Modified widlar source and logic circuit using same

A memory (20) for performing read cycles and write cycles has memory cells (30) located at intersections of word lines (32) and bit line pairs (34). A write control circuit (44) receives a write enable signal. The logic state of the write enable signal determines whether memory (20) writes data into, or reads data from, memory (20). Memory (20) includes row address decoding for selecting a word line (32). During a write cycle, a control signal generated by write control circuit (44) and single-sided delay circuit (45) is provided to row predecoder (42). The old row address is latched, and a new address is prevented from selecting a new word line (32) until the write enable signal changes state to begin a read cycle. Controlling word line selection with the write enable signal ensures that bit line equalization occurs before the beginning of a read cycle.

Memory having a write enable controlled word line

A memory (20) has a read cycle and a write cycle. During the read cycle, differential data signals, corresponding to data provided by a selected memory cell, are superimposed on a first common mode voltage and provided to data output buffers (70-73). During the write cycle, differential data signals on read global data lines (61-62) are equalized at a second common mode voltage and data output buffers (70-73) are disabled. Output enable circuit (74) provides an output enable signal halfway between the first and second common mode voltages. Data output buffers (70-73) are enabled at the beginning of the read cycle when the differential data signals cross the output enable signal as they transition from the second common mode voltage to the first common mode voltage. Enabling data output buffers (70-73) in this way greatly relaxes output enable timing constraints.

Memory having output buffer enable by level comparison and method

A BICMOS memory performs address transition detection on each address signal. A first ECL difference amplifier detects a low-to-high transition with a first input being the address signal, and a second input being the address signal delayed and level-shifted. A second ECL difference amplifier uses a complement of the first and second inputs to detect a high-to-low transition. The outputs of two corresponding ECL difference amplifiers for each address signal are wire-ORed together to form the address transition detection signal, which is delayed for first, second, and third predetermined times to sequentially perform row predecoding, row decoding, and block decoding, respectively. The decoding is performed by logic circuits using modified Widlar current sources, which decrease the current required except during decoding, as indicated by a corresponding address transition detection signal. The saving in current allows faster ECL circuits to be used and decreases peak current on internal power supply lines.

Low power BICMOS memory using address transition detection and a method

An integrated circuit memory with improved di/dt control. The memory stores a plurality of data bits at intersections of word lines and bit line pairs. In response to a change in at least one of a plurality of address signals during a read cycle, first and second precharge signals are asserted, the second precharge signal asserted after the first precharge signal. An output buffer provides a data output signal at a voltage between a logic high and a logic low voltage in response to an assertion of the second precharge signal, and provides said data output signal corresponding to a voltage on an enabled bit line pair in response to a negation of the first precharge signal. Thus, the voltage on the data output signal changes less when the data bit is provided during the data period. The memory thus improves di/dt for a given access time, or conversely, allows reduced access time for a given di/dt.

Integrated circuit memory with improved di/dt control

A memory uses address transition detection to reduce power consumption of the output amplification stage. The output amplification stage, which drives an output driver, has a series of stages which are disabled except when there is an address transition. When there is an address transition all of the stages are quickly enabled except the last stage. The last stage has its output clamped to an invalid state when the other stages are first enabled and then is enabled a predetermined time after the other stages are enabled. The output of the last stage is sensed by a detector. After the last stage has been enabled and is providing valid data, the detector detects that the output of the last stage is valid, and the series of stages are all disabled. The output driver latches the data and provides an output. The output stage is thus disabled and thus not wasting power except during the portion of a cycle when there is actual need for amplification. The stage at which valid data is detected, which is the last stage, is clamped and disabled at the beginning of the cycle to ensure that the detector does not detect, as being valid, data that is invalid.

Output amplifying stage with power saving feature

An output buffer in an integrated circuit comprising voltage regulator, a predriver, and an output stage. The integrated circuit comprises a chip and a package and interconnections therebetween. The voltage regulator is coupled to a first power supply voltage terminal and a second power supply voltage terminal, and provides a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations in voltage between the first power supply voltage terminal and the second power supply voltage terminal. The predriver receives the regulated voltage signal and a data input signal and provides a regulated predriven signal in response to the data signal. The output stage receives the regulated predriven signal and provides an output signal in response thereto. The output signal is driven onto a bonding pad of the device to provide an interconnection point between the chip and the package.

Low di/dt output buffer with improved speed

A multiple element integrated circuit trench cell having at least one vertical field effect transistor (FET) in a wall of a trench in a semiconductor substrate. The cell further comprises a central load device within the trench which is electrically connected to the vertical FET. The central load device may be an active load device, such as another field effect transistor, or a passive load device, such as a resistor. Additionally, a further FET may be present in another wall of the trench or in a lateral orientation adjacent the trench in the semiconductor surface. Two of these multiple element trench cells may be interconnected in various configurations to form conventional static random access memory (SRAM) cells.

Integrated circuit trench cell

A semiconductor memory device having a divided word line architecture in which each block of the memory array is divided into half-blocks and the half-blocks of each block are located on different halves of the device separated by the row decoder. A data line bussing scheme cooperates with this unique organization of the memory array to provide for sense amplifier sharing. This feature allows fewer, and larger sense amplifiers for better performance.

Semiconductor memory with divided word lines and shared sense amplifiers

In a random access memory a write driver develops a full rail write signal which is coupled to the selected bit line pair via transmission gates. The bit lines are thus driven to full rail. This results in a faster rise time on the bit line which is driven to a logic high. With the faster rise time, the selected cell is written into more quickly with the result of a faster write time for the memory.

High speed write technique for a memory

A memory has a memory cells located at intersections of bit line pairs and word lines. During a write mode of the memory, the bit lines are at a maximum voltage separation. For a read to occur following a write, the bit lines must first be equalized. Because of the extent of the voltage separation during a write, equalizing the bit lines can cause a large peak current drain on the power supply. This peak current is reduced by partially charging the bit lines in response to a write to read transition then bringing the bit lines to the final equalization voltage in response to a transition of the row address. The partial charging is ensured of occurring first in the event that the write to read transition occurs simultaneously with a row address transition to ensure a reduced peak current.

Bit line equalization in a memory

A memory has a read mode in which data is read from a bit line pair selected by a column address and a write mode in which data is written onto a selected bit line pair. The selected bit line pair is coupled to a data line pair via a column decoder in response to a column address. Upon a transition from the write mode to the read mode the column decoder is disabled from coupling the selected data line to the data line pair for the duration of a column disable pulse. The column disable pulse is generated in response to a write transition pulse or a column transition pulse or both. The column transition pulse is generated in response to a change in the column address. The write transition pulse is generated in response to a write to read transition.

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Austin, TX, United States of America

Karl L Wang