Micron Technology Incorporated

Karl L Major

Boon Hor Lam

Shawn M Hilde

Galaly Ahmad

Jonathan Hawkins

Garrett Harwell

Dennis G Montierth

Aaron M Baum

Mark Eyolfson

Loon Ming Ho

Xueqing Sun

Chris Langworthy

Travis Marley

Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder.

Apparatuses including temperature-based threshold voltage compensated sense amplifiers and methods for compensating same

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.

Semiconductor device with selective command delay and associated methods and systems

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may disable ECC functions of the memory devices. When the ECC function is disabled by the host device, the memory device may deactivate various ECC periphery components coupled with an ECC circuit of the memory device to reduce power consumption of the memory device. In some cases, the memory device may disconnect an electrical power supply to the ECC periphery components. In other cases, the memory device may selectively disable the ECC periphery components or block an access command from reaching the ECC periphery components during an access operation. Further, the ECC array may be configured to replace faulty portions of a main array of the memory device when the ECC function is disabled.

Semiconductor device with power-saving mode and associated methods and systems

In some examples, an inactive word line voltage control (IWVC) circuit may be configured to provide a respective subword driver associated with a memory bank of a plurality of memory banks a non-active potential from a default off-state word line voltage (VNWL) to a reduced voltage VNWL lower than the default VNWL following a time duration after activating the memory bank. The IWVC circuit may also be configured to provide the respective subword driver with the default VNWL responsive to precharging the memory bank. The IWVC circuit may include a multiplexer coupled to the subword driver and configured to provide the default VNWL or the reduced voltage VNWL to the respective subword driver responsive to a VNWL control signal. The IWVC circuit may also include a time control circuit configured to provide the VNWL control signal responsive to a clock signal and a time control signal.

Apparatuses and methods for reducing access device sub-threshold leakage in semiconductor devices

A system and method to perform analysis on test results of multiple integrated circuits. Based on the analysis, the system and method display a wafer map having map indicators representing statistical values of the test results.

System and method for analyzing electrical failure data

The present invention provides a method and apparatus for equilibrating paired digit lines and sense amplifier input of a memory device, particularly useful where one side of a memory array contains a defect. A pair of isolation circuits is arranged on either side of a sense amplifier between the sense amplifier and respective digit lines pairs from two memory arrays. By selectively enabling one and then the other of the isolation circuits in a multiplexed fashion, the single equilibrate circuit located between one of the isolation circuits of the sense amplifier can separately and sequentially equilibrate both pairs of digit lines. In addition, both isolation circuits can be disabled isolating the sense amplifier from all digit lines allowing the sense amplifier to be separately equilibrated.

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Boise, ID, United States of America

Karl L Major