Siemens Aktiengesellschaft

Siemens Aktiengellschaft

Karl Knauer

Hans-Joerg Pfleiderer

Hans J Pfleiderer

Winfried Kamp

Juergen Pandel

Ulrich Ramacher

Jenoe Tihanyi

Max Schlichte

Hans-Jorg Pfleiderer

Guenther Meusburger

Asynchronous logic circuit for 2-phase operation

Logic circuit for asynchronous circuits with n-channel logic block and

A digital neural network has a plurality of neurons (NR) completely meshed with one another, each of which comprises an evaluation stage having a plurality of evaluators (B) that is equal in number to the plurality of neurons (NR) and each of which comprises a decision stage having a decision unit (E). An adjustment information (INF.sub.E) that effects a defined pre-adjustment of the decision unit (E) can be supplied to every decision unit (E) by a pre-processing means via an information input. A weighting information (INF.sub.G) can be supplied to every evaluator (B) by a pre-processing means via an individual information input. An output information (INF.sub.A) can be output by every decision unit (E) to a post-processing means via a respective individual information output. The information outputs of the decision units (E) are each connected to an individual processing input of all evaluators (B) allocated to the appertaining decision unit (E). Individual processing outputs of the evaluators (B) are connected to individual processing inputs of the decision unit (E) in the appertaining neuron (N), so that every output information (INF.sub.A) can be indirectly fed back onto every neuron (NR).

Digital neural network executed in integrated circuit technology

A network architecture for the programmable emulation of large artificial neural networks ANN having digital operation employs a plurality L of neuron units of identical structure, each equipped with m neurons, the inputs (E) thereof being connected to network inputs (E.sub.N) multiplied or branching via individual input registers (REG.sub.E). The outputs (A) of the neuron units are connectable to network outputs (A.sub.N) at different points in time via individual multiplexers (MUX) and individual output registers (REG.sub.A) and the neuron units have individual auxiliary inputs via which signals can be supplied to them that represent weighting values (W) for weighting the appertaining neural connections and represent thresholds (0) for weighting input signals.

Network architecture for the programmable emulation of artificial neural

A carry-select adder composed of blocks, each containing an input adder cell and a number of adder cells of a first and second type. Each block has one input adder cell interconnected to adder cells of the first and second type which are connected in an alternating fashion. The cells are connected to each other via carry lines and block carry lines. The adder cells of the first and second type each have a gate arrangement which utilizes field effect transistors for transfer, pull-up and pull-down transistors. These transistors are not a component part of a combination gate within an adder cell. The gate arrangement significantly increases the processing speed of the carry-select adder.

Carry-select adder

A multi-place ripple-carry adder adapted for CMOS technology incorporates two types of adder cells in which the adder cells of a first type receive two operand inputs and an inverted carry input signal and produce outputs corresponding to a sum signal and a non-inverted carry output signal. The adder cells of the second type accept two operand inputs and produce, as outputs, a sum signal and a non-inverted carry output signal. The gate arrangements of the adder cells of each type are designed so that the capacitance of the carry output is charged through either one transfer transistor acting as a transfer gate, or through a series connection of two transistors of which one transistor acts as a transfer gate. Both binary values can be transmitted as inverted and non-inverted carry output signals without additional threshold voltage losses. The transfer transistors in the carry propagation path are not component parts of a combination gate within the gate arrangement, so that they can be designed with lower impedance than the remaining transistors, resulting in faster rise times for the output pulses.

Multi-place ripple-carry adder

An adder cell in which the sum signal and the carry signal are formed with equal speed is provided for employment in 'carry-save' adders, wherein the sum signal and the carry signal are separately forwarded to separate inputs of following adder cells. The circuit of the adder cell is designed such that the sum signal as well as the carry signal each have to traverse only two gates, so that the running times of sum signal and carry signal are approximately identical and shorter than the maximum running time of conventional adder cells.

Adder cell for carry-save arithmetic

An adder cell for a ripple-carry adder, suitable for use in an integrated circuit employing CMOS technology, has a gate arrangement for two input variables and a carry input signal, with outputs for sum and carry signals, in accordance with the signals presented to the inputs. The gate arrangement is arranged so that the charging of the capacitance of the carry output takes place from a supply voltage through two transistor gates, not contained in a combination gate, so that one of the transistor gates may be formed as a driving inverter separate from the time-critical carry-propogation path, and designed with significantly lower impedance than the other transistor gates. Alternatively, a single transistor gate is employed for charging the capacitance of the carry output directly form a supply voltage.

Ripple-carry adder

A transversal filter has an analog shift register exhibiting a series input and a plurality of parallel outputs which are connected to a summing and/or subtracting circuit. A simple realization of signal weighting circuits assigned to the stages of the shift register is achieved in that n signal weighting devices assigned to a group of n stages are disposed in a signal path which extends from the input of the first stage of the group over all stages thereof and in that the signal weighting devices of the n stages respectively weight according to filter coefficients b.sub.1 -b.sub.n which occur in the system function

Transversal filter having an analog shift register

A transversal filter with an analog shift register has a plurality of parallel inputs and a serial output at which a filtered signal appears. An object is to provide as simple as possible a realization of the n signal evaluators allocated to the n stages of the shift register. This is achieved by providing the n signal evaluators in a signal path proceeding from the input of the first stage over all n stages, and to evaluate according to evaluation factors b.sub.n through b.sub.1 which occur in the system function

Transversal filter having parallel inputs

An input stage for a monolithically integrated charge transfer device of the type which generates two complementary charge packets from one input signal, said input stage having at least two transfer gates disposed between a source region in a semiconductor body and an input gate which is charged with the input signal. The two transfer gates in the input stage are connected to clock pulse voltages which operate at one half the clock frequency of the transfer stages covering the transfer channel of the charge transfer device. A particularly low-noise encoding of the input signal into the two complementary charge packets results thereby and the structure is particularly suitable for analog signal processing.

Input stage for a monolithically integrated charge transfer device which

The invention relates to an input stage for a charge transfer device (CTD) arrangement which contains a source zone in a semiconductor body, two input electrodes, and a transfer gate, wherein one input gate is connected to a fixed voltage, and the other input gate is supplied with an analog input signal. In input stages of this kind, it is endeavored to evaluate the input signal within the widest possible limits without the need of altering the assigned semiconductor surface. The invention achieves this aim in that the input stage is divided into two input channels which possess different widths and which open into the CTD channel. A positive evaluation of the input signal is carried out via the first input channel, whereas a negative evaluation is carried out via the second input channel. The difference in area between the second input gate electrodes of the two input channels represents a gauge of the evaluation coefficient and can be kept very small. The range of application of the invention covers arbitrary CTD circuits, and in particular CTD transversal filters.

Input stage for a charge transfer device (CTD) arrangement

The invention relates to a CTD arrangement comprising an input stage (ETS) which increases each of the input, signal-dependent charge quantities by basic charges (fat zero). In arrangements of this kind, it is endeavored to eliminate the influence of fluctuations in operating voltages upon the d.c. voltage component or d.c. component of the output signal. The invention solves this problem in that a compensation stage (KST) which fully eliminates the added basic charges is inserted into the CTD channel. The sphere of application for the invention includes CTD circuits, and in particular CTD transversal filter circuits.

Input charge corrected monolithically integrated charge transfer device

A dynamic element is disclosed which is constructed on a doped semiconductor substrate. A strip-shaped semiconductor region, which is on a surface of the substrate and which is doped opposite to the substrate, is designed as a first selection line, whereas a path which is separated by means of an insulating layer from the substrate, and which runs cross-wise to the strip-shaped region, represents a second selection line. The path is separated from a substrate region which lies next to the strip-shaped region by means of a thin film region of the insulating layer. In the case of memory elements of this type, simple construction and small dimensions are desired. According to the invention, this is achieved in that inside of the strip-shaped region, an island-shaped semiconductor region doped opposite to the strip-shaped region is arranged and which lies close to an interface of the strip-shaped region separating it from the semiconductor region which lies under the thin film region. The invention is useful in digital semiconductor memories of high bit density.

Highly integrated dynamic memory element

A CTD transversal filter is disclosed which comprises a CTD arrangement with parallel inputs and evaluation circuits. The evaluation coefficients are set up in digital fashion by means of comparator-controlled input sequences of signal-dependent quantities of charge. High value coefficients may be established without the need to reduce a lower frequency transmission limit. With the invention, the transfer electrodes of the CTD are not supplied with the normal clock voltages but with the output voltages of a shift register in which circulates an item of logic information which forwards the input charges individually and consecutively by one electrode spacing. The application of this 'electrode-per-bit' operation results in a considerable increase in the times for the individual input sequences. The invention is useful in programmable frequency filters.

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Grafing, Germany

Karl Knauer