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Infineon Technologies Ag

Karl J Zapf

Kurt Hoffmann

Thomas Kuenemund

Christian Pacha

Siegmar Köppe

Artur Wroblewski

A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means which hold a logic hold level to be tapped off as a stored logic state of the logic signal. The logic hold level is adjustable to a first logic level by a first push-pull transistor controlled by the set signal and to a second logic level by a second push-pull transistor controlled by the reset signal.

Pulsed static flip-flop

An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.

Masked memory cells

MOS integrated circuit arrangement for suppressing quiescent currents flowing in word line drivers of semiconductor memories, including respective controlled switches addressed by a storage activation signal, the controlled switches being connected between the output circuit of the word line drivers and reference potential.

MOS-Integrated circuit arrangement for suppressing quiescent currents

A clock-controlled dc converter is provided in integrated semiconductor MOS technology and serves the supply voltage of integrated MOS circuits, particularly dynamic memories. The converter comprises a clock pulse generator having two outputs, supplying sequences of clock pulses which are inverted with respect to one another, which pulses are connected to the two clock pulse inputs of a first pulse level shifter. The first pulse level shifter comprises a bistable flip-flop lying at a supply potential, and which is switched as a level shifter. The two outputs of the first level shifter are connected, on the one hand, to the output of a voltage converter by way of the source-drain circuit of a respective field effect transistor. On the other hand, the two outputs are connected to the supply input of a respective pulse voltage doubler, which are in turn directly charged by a respective output of the clock pulse generator. The two pulse voltage doublers supply the clock pulse supply for a second pulse level shifter, likewise constructed as a bistable flip-flop, by way of the two outputs of which the connection between the outputs of the first level shifter and the output of the voltage comparator is controlled. The doubled supply voltage appears at the output of the voltage converter.

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Munich, Germany

Karl J Zapf