University of Illinois

Karl Hess

Joseph W Lyding

James J Coleman

Hadis Morkoc

Jinju Lee

Mark A Emanuel

Ted K Higman

Ben G Streetman

Described are preferred processes for conditioning semiconductor devices with deuterium to improve operating characteristics and decrease depassivation which occurs during the course of device operation. Also described are semiconductor devices which can be prepared by such processes.

Semiconductor devices, and methods for same

Semiconductor device annealing process with deuterium at superatmospheric pressures to improve reduction of the effects of hot carrier stress during device operation, and devices produced thereby.

Deuterium treatment of semiconductor device

Semiconductor devices and methods for same

Forming of deuterium containing nitride spacers and fabrication of

Deuterium-treated semiconductor devices

A semiconductor heterostructure device is disclosed which includes a first semiconductor layer having a barrier layer disposed thereon, the barrier layer being formed of a semiconductor material having a wider bandgap than the material of the first semiconductor layer. A carrier transport layer is disposed on the barrier layer, the carrier transport layer being formed of a semiconductor material having a narrower bandgap than the material of the barrier layer. A contact layer is disposed on the carrier transport layer. A negative potential is applied to the contact layer with respect to the first semiconductor layer. In operation, for small voltages, under the indicated bias configuration, electrons supplied to the carrier transport layer by the source of negative potential supply will be blocked at the barrier presented by the larger bandgap barrier layer, and little current will flow. As the bias voltage is increased, these blocked electrons are under the influence of

Semiconductor device and method

Described is a heterostructure semiconductor device of sandwich type construction. The central layer exhibits high charge carrier mobility and a relatively narrow band gap characteristic. The outer sandwich layers exhibit low charge carrier mobilities and a larger band gap characteristic. Under quiescent conditions, the charge carriers from the outer sandwich layers reside in the central layer due to the 'potential well' created by the band gap difference between the layers. The application of an appropriate electrical field to the central layer, aligned with the interface between the layers, causes a very rapid transfer of the electrons residing therein to the outer sandwich layers. This transfer results in the device exhibiting a negative resistance characteristic. Two and three terminal switching applications of the device are described as well as its application as a radiant energy detector.

Negative resistance heterojunction devices

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Champaign, IL, United States of America

Karl Hess