Disco Hi-tec Europe Gmbh

Takatori Corporation

Infineon Technologies Ag

Karl Heinz Priewasser

Ken Ikehata

Yoshinori Kakinuma

Yosuke Ishimatsu

Sylvia Baumann Winter

Ryouta Sawayama

Yoshiyuki Harioka

To perform alignment of a protective tape having a protective layer with high accuracy, provided is an alignment device () to be used for applying a protective tape (PT) to a semiconductor wafer (W), including: a tape holding body () configured to hold the protective tape (PT) laminated with a protective layer (PL) having an outer diameter smaller than an outer diameter of the protective tape (PT), and one image pickup means () for imaging a plurality of parts of an outer peripheral edge portion of the protective layer (PL), wherein the alignment device is configured to determine a center position of the protective layer (PL) based on positional information on each of the plurality of parts of the outer peripheral edge portion of the protective layer (PL) through determination of the positional information on the each of the plurality of parts based on image data acquired by imaging of the image pickup means ().

Alignment device and alignment method

To satisfactorily apply a protective tape to a bump wafer, an application apparatus () for applying a protective tape (PT) to a wafer (W) includes: an application table () configured to support the wafer (W); a tape holding body () capable of holding the protective tape (PT) and configured to supply the protective tape (PT) held by the tape holding body () onto the wafer (W); and a pressing member () configured to press the protective tape (PT) from above. The pressing member () includes a protective layer outer periphery retainer () configured to press a peripheral portion of a protective layer (PL), which is laminated on the protective tape (PT) and has an outer diameter smaller than an outer diameter of the wafer (W), to apply the protective tape (PT) to the wafer (W).

Device and method for attaching protective tape on semiconductor wafer

To reduce residual stress generated on a protective tape at a time of application of the protective tape to a semiconductor wafer, provided is an application apparatus () for applying a protective tape (PT) to a semiconductor wafer (W), including: a tape conveyance mechanism () configured to convey the protective tape (PT) temporarily applied to a base material (BM) to a peeling position; a tape holding body () capable of holding the protective tape (PT); a holding-body moving mechanism () configured to move the tape holding body () to the peeling position; and a peeling mechanism () configured to peel the base material (BM) from the protective tape (PT) held by the tape holding body () at the peeling position.

Device and method for attaching protective tape to semiconductor wafer

Disclosed is a method for generating chip stacks during the production of chips from wafers, the chips located on the wafer being separated from one another, the wafer being ground thin and the chips being stacked to form chip stacks, the chips being checked for the purpose of a functional check, characterized in that the chips are checked in a first work step, that adhesive material is applied on the good chips, whereas the bad chips are not provided with adhesive material, that the wafer is assembled and ground thin afterwards and that the bad chips are subsequently removed and replaced by good chips.

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Kirchheim, Germany

Karl Heinz Priewasser