Infineon Technologies Dresden Gmbh

Infineon Technologies Ag

Karl-Heinz Gebhardt

Andreas Peter Meiser

Till Schloesser

Marc Strasser

Detlef Weber

Ralf Rudolf

Lincoln O'Riain

A semiconductor device and a method of manufacturing the same is provided. The semiconductor device including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.

Semiconductor device comprising a transistor cell including a source contact in a trench, method for manufacturing the semiconductor device and integrated circuit

A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.

Method for manufacturing an integrated circuit including a lateral trench transistor and a logic circuit element

A semiconductor device is provided including a transistor cell in a semiconductor substrate having a first main surface. The transistor cell includes a gate electrode in a gate trench in the first main surface adjacent to a body region. A longitudinal axis of the gate trench extends in a first direction parallel to the first main surface. A source region, a body region and a drain region are disposed along the first direction. A source contact comprises a first source contact portion and a second source contact portion. The second source contact portion is disposed at a second main surface of the semiconductor substrate. The first source contact portion includes a source conductive material in direct contact with the source region and a portion of the semiconductor substrate arranged between the source conductive material and the second source contact portion.

A semiconductor device includes an electrode arranged on a main surface of a semiconductor body and an insulating structure insulating the electrode from the semiconductor body. The insulating structure includes in a vertical cross-section a gate dielectric portion forming a first horizontal interface at least with a drift region of the device and having a first maximum vertical extension between the first horizontal interface and the electrode, and a field dielectric portion forming with the drift region second, third and fourth horizontal interfaces. The second through fourth horizontal interfaces are arranged below the main surface. The third horizontal interface is arranged between the second and fourth horizontal interfaces. A second maximum vertical extension is larger than the first maximum vertical extension and a third maximum vertical extension is larger than the second maximum vertical extension. The electrode only partially overlaps the third horizontal interface.

Semiconductor device with an insulating structure for insulating an electrode from a semiconductor body

A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A lateral isolation layer is disposed in the isolation trench. The semiconductor device further includes a source region and a drain region, and a body region and a drift region disposed between the source region and the drain region. The semiconductor device additionally includes a gate electrode adjacent to at least a portion of the body region and a field plate adjacent to at least a portion of the drift region. A field dielectric layer is disposed between the drift region and the field plate. A top surface of the field dielectric layer is disposed at a greater height measured from a first main surface of the semiconductor substrate than a top surface of the lateral isolation layer.

Semiconductor device and method of manufacturing a semiconductor device

A method produces a semiconductor device including a semiconductor body, an electrode thereon, and an insulating structure insulating the electrode from the semiconductor body. The semiconductor body includes a first contact region of a first conductivity type, a body region of a second conductivity type, a drift region of the first conductivity type, and a second contact region having a higher maximum doping concentration than the drift region. The insulating structure includes a gate dielectric portion forming a first horizontal interface. with the drift region and has a first maximum vertical extension A field dielectric portion forms with the drift region second and third horizontal interfaces arranged below the main surface. A second maximum vertical extension of the field dielectric portion is larger than the first maximum vertical extension. A third maximum vertical extension of the field dielectric portion is larger than the second maximum vertical extension.

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Dresden, Germany

Karl-Heinz Gebhardt