Texas Instruments Corporation

Nvidia Corporation

Karl Friedrich Greb

Balatripura Chavali

Rajeev Suvarna

Nicholas H Schutt

Michael Truog

Sunil Suresh Oak

Kevin Patrick Lavery

Alexandre Pierre Palus

Hari Unni Krishnan

Yanyang Xiao

Paul William Krause

Bhavesh Parekh

Krishna Sitaraman

Mitchell Darren Luban

David Nister

Gary D Hicok

Henry Nguyen

Jonathan Sweedler

John George Mathieson

Ram Ganapathi

Ashok Srinivasan

Clement Farabet

Mohammed Abdulla Yousuf

Michael Alan Ditty

Mike Truog

Kevin Flory

Daniel Stewart Perrin

Tai-Yuen Chan

Gerhard Michael Wenderlein

Dan Hettena

TY Chan

Daniel Perrin

Diagnostics and boot up for AV hardware and software of a computer system of an autonomous vehicle may be performed based at least on receiving a shutdown or power off indication, then a computing state of the computer system may be suspended with the computer system entering a low-power mode. The suspended computing state can be rapidly restored without requiring a reboot and diagnostics for key-on. To ensure the integrity of the saved computing state, the computer system may exit the low-power mode, rerun the diagnostics, reload the programs, and then reenter the low-power mode. Restoring the suspended computing state may be triggered by a user inserting an ignition key, pressing a button to turn on the vehicle, opening a door to the vehicle, remotely unlocking the vehicle, remotely starting the vehicle, etc.

State suspension for optimizing start-up processes of autonomous vehicles

Autonomous driving is one of the world's most challenging computational problems. Very large amounts of data from cameras, RADARs, LIDARs, and HD-Maps must be processed to generate commands to control the car safely and comfortably in real-time. This challenging task requires a dedicated supercomputer that is energy-efficient and low-power, complex high-performance software, and breakthroughs in deep learning AI algorithms. To meet this task, the present technology provides advanced systems and methods that facilitate autonomous driving functionality, including a platform for autonomous driving Levels 3, 4, and/or 5. In preferred embodiments, the technology provides an end-to-end platform with a flexible architecture, including an architecture for autonomous vehicles that leverages computer vision and known ADAS techniques, providing diversity and redundancy, and meeting functional safety standards. The technology provides for a faster, more reliable, safer, energy-efficient and space-efficient System-on-a-Chip, which may be integrated into a flexible, expandable platform that enables a wide-range of autonomous vehicles, including cars, taxis, trucks, and buses, as well as watercraft and aircraft.

Systems and methods for safe and reliable autonomous vehicles

A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task.

System and method for per-task memory protection for a non-programmable bus master

An electronic circuit includes a microcontroller processor (), a peripheral () coupled with the processor, an endian circuit () coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit () to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Endian configuration memory and ECC protecting processor endianess mode circuit

A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

System and method for virtual hardware memory protection

A video output supervisor includes a test region indicator for verifying that the commanded output to specific areas of a display is valid. Areas reserved displaying safety-critical data in the data frame to be displayed can be supervised for the presence and status of display indicators of the safety-critical data. The confidence of the supervision can be increased by measuring other display and frame parameters in conjunction with supervising the indicators of the safety-critical data.

Video output supervisor

Encode and multiplex, register, and decode and error correction circuitry

An independently based diagnostic system tests the execution of a processor. The processor is arranged to provide a diagnostic output that provides a pre-determined time-variant signal. The independently based diagnostic system has an independent basis from which to evaluate the pre-determined time-variant signal. The independent basis can be, for example, an independent time base that is separately generated from the processor time base used to clock the processor and/or an independent voltage source that is separate from the processor power supply. The independently based diagnostic system provides progressive notifications of the results of successive evaluations of the pre-determined time-variant signal.

Independently based diagnostic monitoring

An error monitor receives a first list of selected system events with each selected system event having an associated range. The occurrence of each selected system event is counted over a selected time period. An error indication is provided based on a comparison of each of the counts of the occurrence of each selected system event over the selected time period with the associated range. Operational profiles are used to store lists of selected system events with each selected system event having an associated range for each operational profile.

Event monitor having switch matrix, separate counter, and compare circuitry

An integrated circuit includes a first multiplexer (mux) with multiple inputs and configured to produce a mux output signal. The electronic circuit also includes a first gated buffer to receive the mux output signal from the first multiplexer and produce a first gated buffer output signal, a second gated buffer to receive the first gated buffer output signal and to produce a second gated buffer output signal to be provided to a pin, and a receive buffer. The receive buffer is coupled to the pin and receives an input signal from the pin. The electronic circuit operates in a test mode in which the second gated buffer is disabled preventing a test signal provided to an input of the first mux from reaching the pin. Instead, the test signal is provided through the first mux to the first gated buffer and to the receive buffer thereby testing the first mux.

Testing for multiplexer logic associated with a multiplexed input/output pin

A system comprises built-in self-test (BIST) logic configured to perform a BIST, processing logic coupled to the BIST logic and storage logic coupled to the processing logic. The storage logic comprises debug context information associated with a debugging session. Prior to performance of the BIST, the processing logic stores the debug context information to a destination. After performance of the BIST, the processing logic is reset, and the processing logic restores the debug context information from the destination to the storage logic.

Saving debugging contexts with periodic built-in self-test execution

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Sugar Land, TX, United States of America

Karl Friedrich Greb