International Business Machines Corporation

Karl Evan Smock Anderson

Christian Jacobi

Alper Buyuktosunoglu

Tobias Webel

Sean Michael Carey

Chung-Lung K Shum

Phillip John Restle

Andrew A Turner

Eberhard Engler

Edward C McCain

Kennedy K Cheruiyot

Pradeep Bhadravati Parashurama

Alejandro Alberto Cook Lobo

Kevin P Low

Daniel Kiss

Isidore G Bendrihem

Ian Krispin Carmichael

Anthony Saporito

Patrick James Meaney

William Vincent Huott

Adam B Collura

Gregory Scott Still

Michael J Cadigan, Jr

Stefan Payer

Bodo Hoppe

Pawel Owczarczyk

Eric Jason Fluhr

Benjamin Neil Trombley

Shiri Moran

Douglas G Balazich

Erica Stuecheli

Paul Jacob Logsdon

Michael Romain

Arvind Haran

Mark Cichanowski

Error protection analysis of an integrated circuit includes receiving a design model for the integrated circuit, and a list of error checkers associated with the design model. The design model is traversed from each of the error checkers to group storage cells of the design model into checking groups. The design model is updated to include, for each checking group, a unique group identifier associated with each of the storage cells in the checking group.

Error protection analysis of an integrated circuit

Embodiments include in response to monitoring a processor during operation, detecting a first number of throttling amounts in the processor, determining that the first number of throttling amounts fulfills a first condition regarding a throttling amounts threshold, and modifying a voltage level of the processor by a first amount. Embodiments include in response to modifying the voltage level of the processor by the first amount, detecting a second number of throttling amounts in the processor, determining that the second number of throttling amounts fulfills a second condition regarding the throttling amounts threshold, and modifying the voltage level of the processor by a second amount.

Dynamic guard band with timing protection and with performance protection

Embodiments include in response to monitoring a processor during operation, detecting a first number of core recovery events in the processor, determining that the first number of core recovery events fulfills a first condition for the first core recovery events threshold, and modifying a value of at least one droop sensor parameter of the processor by a first amount. The at least one droop sensor parameters affects a sensitivity to a voltage droop. In response to modifying the value of the droop sensor parameter by the first amount, a second number of core recovery events is detected in the processor. It is determined that the second number of core recovery events fulfills a second condition for a second core recovery events threshold, and the value of the at least one droop sensor parameter is modified by a second amount.

The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Method to limit the time a semiconductor device operates above a maximum operating voltage

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Poughkeepsie, NY, United States of America

Karl Evan Smock Anderson