Cirrus Logic Inc.

Philips Lighting Holding B.v.

Cirrlus Logic, Inc.

Karl Ernesto Thompson

John L Melanson

Eric J Swanson

Wai Laing Lee

Douglas S Piasecki

Carlos Esteban Mu&ntilde;oz

Ammisetti Prasad

Mauro L Gaetano

Erik J Mentze

Shyam S Somayajula

Chung-Kai Chow

Michael Allan Kost

John James Paulos

Jason Powell Rhode

Kartik Nanda

Trenton John Grale

Carlos Estaban Mu&ntilde;oz

Ammisetti V Prasad

John Laurence Melanson

Power consumption in a start-up circuit for a LED-based light bulb may be reduced by digitally switching a transistor of the start-up circuit coupled to the input voltage. When the transistor is digitally switched between on and off, a reduced amount of power is dissipated by the transistor, because it may not enter a saturation region of operation where the resistance of the transistor between drain and source terminals increases. The transistor may be coupled to a voltage regulator for generating one or more output voltages, including a supply voltage for a host controller IC. The transistor may be switched on and off by a digital signal generated by logic circuitry, which may decide to switch the transistor on and off based on a voltage level at an output of the voltage regulator.

Digitally-controlled switch-mode start-up circuit for LED-based lights

Digitally-controlled switch-mode start-up circuit with dimmer compatibility for LED-based lights

A system and method reduces power consumption by an electronic power control system when a controller of the electronic power control system reduces sense signal monitoring during a standby mode of the controller. The electronic power control system includes a controller to control a switching power converter. The controller operates in at least two modes, standby and active modes. Energy savings during standby mode can be achieved in a variety of current and/or voltage sensing configurations. During the standby mode, the controller generates a signal to at least intermittently disable sensing of an input voltage to the switching power converter or at least intermittently disabling sensing of an input voltage and an output voltage. Disabling sensing reduces energy losses associated with an input voltage sense signal itself and with circuitry in the controller used to process the input voltage signal.

Reduced standby power in an electronic power control system

A power supply system and method includes a switch state controller that is operational to control a switching power converter during certain power loss conditions that cause conventional switch state controllers to have diminished or no functionality. In at least one embodiment, during certain power loss conditions, such as when an auxiliary power supply is in standby mode or when the switching power converter is not operating, a power supply for the switch state controller does not provide sufficient operating power to the switch state controller during certain power loss conditions. In at least one embodiment, during such power loss conditions power is generated for the switch state controller using sense input and/or sense output currents of the switching power converter to allow an integrated circuit (IC) switch state controller to generate a control signal to control a switch of the switching power converter.

Switch state controller with a sense current generated operating voltage

A power control system and method senses input and/or output voltages of a power supply using sense currents in order for an integrated circuit (IC) switch state controller to generate a control signal to control a switch of the power control system. By sensing sense currents, the power control system can eliminate at least one sense resistor used in a voltage sense system. The sense current(s) can be used to provide power and sensing to the switch state controller. In at least one embodiment, the sense current(s) provide power to the switch state controller when auxiliary IC power is unavailable or diminished, such as during start-up of the IC. In at least one embodiment, the IC draws more sense current from an input of the power control system than the output of the power control system to, for example, minimize impact on the output voltage of the power supply.

Powering a power supply integrated circuit with sense current

A boosted auxiliary winding power supply for a switched-power converter circuit provides operating voltage for control and other circuits early in the start-up phase of converter operation. A boost circuit has an input coupled to the auxiliary winding to boost the voltage available from the auxiliary winding at least during start-up of the switched-power converter. The boost thereby provides a voltage that is greater than the voltage across the auxiliary winding during start-up of the switched-power converter. The boost circuit may be actively switched at a rate higher than a switching rate of the switched-power converter, to increase a rate of rise of the operating voltage. Polarity information, which may be provided from the switched-power converter control circuit, can be used to actively rectify the output of the auxiliary winding.

Switching regulator with boosted auxiliary winding supply

A chopping amplifier and method for chopping an input signal are disclosed. The chopping amplifier and method utilize at least two chopping amplifier stages. A chopping operation of an input signal is segmented across two or more chopping amplifier stages, and the two or more chopping amplifier stages are responsive to a master controller. Chop clock signals of the chopping amplifier stages are staggered so that they have non-overlapping periods and at least one of the chopping amplifier stages is not operating in an open loop at any given time. The non-overlapping periods are periodic so that a master chop clock of the master controller can be operated at a lower chop clock frequency. For every doubling of N number of chopping amplifier stages, magnitudes of chopping artifacts and aliased components are each respectively reduced by 3 dB.

Segmented chopping amplifier

A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.

Sample and hold circuits and methods with offset error correction and systems using the same

A data converter includes first and second input signal paths receiving an input signal having an input frequency, the first input signal path dividing the input frequency by a first divisor and the second input signal path dividing the input frequency by a second divisor, the second divisor being greater than the first divisor. A selector selects between an output of the first input signal path and an output from the second input signal path in response to a state of a control signal. Control circuitry monitors a selector output signal frequency and a current state of the control signal and selectively resets the state of the control signal to set the selector output frequency to a desired frequency.

Data conversion circuits and methods with input clock signal frequency detection and master mode output clock signal generation

An auto-calibrating companion bit successive approximation system uses sampling and balancing capacitors in a charge redistribution digital-to-analog converter having multi-valued capacitors of magnitudes enabling redundant expression of electric charge values. Companion bits are used with sets of balancing capacitors for successive approximation of sampling voltages. A charge redistribution digital-to-analog converter has a sampling and balancing capacitors including associated companion bit capacitors represented by digital weights which are saved in memory. A non-binary weighted set of capacitors provides redundancy in a charge redistribution digital-to-analog converter employed in a successive approximation register architecture.

Systems and methods for adaptive auto-calibration of Radix<2 A/D SAR converters with internally generated stimuli

A method of gain scaling in a charge redistribution analog to digital converter includes the step of segmenting a bit weighted capacitor array into a first segment having at least one capacitor representing a least significant bit and a second segment having at least one capacitor representing a most significant bit. During a sampling phase, an input signal is sampled onto the at least one capacitor of the second segment while the at least one capacitor of the first segment is coupled to a fixed voltage.

Analog to digital conversion circuits, systems and methods with gain scaling switched-capacitor array

A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.

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Converse, TX, United States of America

Karl Ernesto Thompson