Motorola Corporation

Freescale Semiconductor,inc.

Infineon Technologies Ag

Other

Infineon Technologies Sc300 Gmbh & Co., Kg

Infineon Technologies Sc300 Gmbh & Co. Ohg

Infineon Technologies Sc300 Gmbh

Karl Emerson Mautz

John George Maltabes

Alain Bernhard Charles

Robert K Berglund

William Mark Hiatt

Thorsten Schedel

Larry E Frisa

Joseph Petrucci

Ralf Schuster

Alain Bernard Charles

Jason S Zeakes

Sebastian Schmidt

Mark Hiatt

Martin Peiter

Eckhard Marx

Jonathan C Dahm

Bruno Spuler

Ralf Zedlitz

Terry Alan Breeden

Iraj Eric Shahvandi

Clinton M Haris

Michael Thomas Tucker

David Weston Haggart, Jr

Barbara Vasquez

Manfred Kraxenberger

Roger Tyldesley

Olivier Gerard Marc Vatel

Jeffrey G Cadenhead

H Adam Stevens

W Mark Hiatt

Ines Th&uuml;mmel

Thomas M Allen

John Dalziel

Graeme Morland

Phil Wootton

The present invention relates to a scribing method for wafers (), wherein a defined beam () is directed onto the wafer () by means of a beam generator means () so as to remove some wafer material from a wafer region. The invention also relates to a wafer-scribing device including a wafer mount () and a beam generator means () by means of which at least one defined beam can be directed onto the wafer (). The inventive method is distinguished by the by the further step of generating a first radiation pulse having a predeterminable energy density and used to create a comparatively deep pit () in the wafer (). The inventive wafer scribing means is distinguished by the provision that a radiation pulse can be generated by means of which a comparatively deep pit () can be created in the wafer ().

Wafer scribing method and wafer scribing device

A lithography and etching method for forming an alignment mark () and at least one device feature (such as a shallow trench) on a wafer () is provided. The etching process () comprises: a first etching step () for pre-defining at least one alignment mark () and a second etching step () for defining desired semiconductor device patterns (such as a shallow trench) on said wafer surface and completing said at least one alignment mark ().

Method for defining alignment marks in a semiconductor wafer

The present invention relates to a system for the manufacture of semiconductor devices by lithography, and in particular to an assembly of mask containers for use in such a system. The system comprises: a plurality of mask containers adapted to engage with one another such that two or more containers can be carried together as a stack; a plurality of lithography bays; a transport rail system for carrying the containers between different lithography bays. Each lithography bay has a transmitter/receiver unit for communicating lithography data with a tracking device located in each container, allowing for more efficient mask management. The transportation of the containers in stacks results in an improvement in efficiency.

Assembly comprising a plurality of mask containers, manufacturing system for manufacturing semiconductor devices, and method

Processing parameters of at least one plate-shaped object, e.g. a semiconductor device or wafer, or a flat panel display, in a processing tool are adjusted depending on which processing device out of at least one set of processing devices has been used for the semiconductor device in a preceding step. A virtual or physical tag is generated, which connects the semiconductor device identification with the processing device identification. This enables a compensation of tool-dependent effects in previous processing of a single device. An example is chemical mechanical polishing prior to lithography, where alignment marks can be deteriorated differently between CMP-units. The amount of compensation is detected and evaluated by metrology tools, which&#x2014;depending on the sequence of the metrology step relative to the processing step to be adjusted&#x2014;either feed-forward or feed-backward their results to the processing tool. The yield of semiconductor device production is advantageously increased.

Method for adjusting processing parameters of at least one plate-shaped object in a processing tool

A process tool, preferably a spin coater, includes a set of at least three arms and an adjustable rinse nozzle. The arms lift a substrate, e.g. a semiconductor wafer, from a chuck inside the process chamber after having performed the corresponding manufacturing step, e.g. coating. The contact area between the arms and the substrate is as small as possible. The rinse nozzle dispenses a solvent liquid onto the backside of the substrate, thereby removing contaminating particles located at the area of contact between the vacuum channels of the chuck and the substrate. The set of arms rotates for a homogeneous cleaning. A gas flowing out of vacuum ports of the chuck prevents the vacuum ports from being obstructed with particles. While the substrate is being lifted, the chuck can also be cleaned by dispensing the solvent liquid onto the chuck.

Configuration and a method for reducing contamination with particles on a substrate in a process tool

An electronic device ( ) is attached to a container ( ) that carries a lithography mask ( ) through a semiconductor factory ( ) form a first station ( ) to a second station ( ). In the device, a receiver unit ( ) receives first data ( ) indicating how the first station has used the mask in a first process; a memory unit ( ) temporarily stores the first data; a processor unit ( ) processes the first data and provides second data ( ) indicating how the second station uses the mask in a second future process; and a transmitter unit ( ) transmits the second data to the second station or to a factory host.

Manufacturing system method for processing a lithography mask container

Method and apparatus for IN SITU measuring a required feature of a layer during a polishing process

A semiconductor wafer ( ), a method of providing information on a semiconductor wafer ( ), a system of semiconductor wafer ( ) and reading means, and a method of reading information from a semiconductor wafer ( ) are provided. The invention is characterized by magnetic means ( ) as information carrier and the respective magnetic sensors ( ) to read such information.

Semiconductor wafer identification

An apparatus for compensating light exposure on different, subsequently irradiated target areas ( ) in a photosensitive medium ( ) on a semiconductor wafer ( ). In order to improve exposure dose uniformity the apparatus comprises a mask filter ( ) with a plurality of oblong transparent ( ) and oblong opaque elements ( ) inserted between a light source ( ) and said photosensitive medium ( ) so that light ( ) traverses through said plurality of transparent elements ( ) to expose the photosensitive medium. Each of said plurality of oblong opaque elements ( ) is rotatable around a longitudinal axis ( ) so as to define the area masked by the projection of the opaque element on the photosensitive medium and to continuously adjust a ratio between irradiated and non-irradiated areas on the photosensitive medium.

Continuously adjustable neutral density area filter

An arrangement for transferring a pattern from a mask ( ) onto a wafer is provided. A product area ( ) of the mask ( ) is at least partly surrounded by a frame ( ) having an alignment mark area ( ). In order to avoid the need to produce a specific mask set for different alignment styles, the mask ( ) and the frame ( ) are designed as being separate units. Further, methods for transferring a pattern from a mask to a wafer are provided that employ a frame separated from a product area.

Arrangement and method for transferring a pattern from a mask to a wafer

A method for monitoring a polishing condition of a surface of a wafer in a polishing process is provided, the method comprising providing a wafer ( ) to be polished, the wafer ( ) having at least one optically distinguishable feature ( ) below a transparent or translucent layer ( ) to be polished; selecting one or more of the features ( ) for monitoring; measuring an optical contrast profile ( ) across one or more of the selected features ( ); determining the polishing condition of the surface of the wafer ( ) on the basis of the measured contrast profile ( ); and repeating the measuring the optical contrast profile ( ) and determining the polishing condition until a predetermined polishing condition is reached. A method for polishing wafers by a CMP polishing tool and apparatus for monitoring a polishing condition of a surface of a wafer ( ) is also provided.

Method and apparatus for monitoring a polishing condition of a surface of a wafer in a polishing process

A semiconductor method for reducing charge damage during plasma etch processing is disclosed. Structures ( ) for accumulating charge during plasma etch processing are provided on a semiconductor wafer ( ), the structures ( ) being electrically connected to device structures ( ).

Semiconductor structure and method for reducing charge damage

The present invention relates to a method of determining a thickness of at least one layer on at least one semiconductor wafer ( ), comprising the steps of: projecting a first laser pulse ( ) on a surface ( ) of the at least one layer ( ), thereby generating an acoustical wave due to heating of the surface of the at least one layer ( ); after a propagation time of the acoustical wave, projecting a series of second laser pulses ( ) on the surface ( ) of the at least one layer ( ); measuring reflected laser pulses ( ) of the second laser pulses ( ), thereby sensing the times of reflection property changes of the surface ( ) of the at least one layer ( ); and determining the thickness of the at least one layer ( ) by analyzing the times of reflection property changes. The present invention further relates to a system for determining a thickness of a layer ( ) on a semiconductor wafer ( ).

Method and system for determining a thickness of a layer

A processing tool bay within a semiconductor fabrication site, including a plurality of semiconductor processing tools for processing wafers being arranged in two opposite rows. An intrabay transport system for transporting wafer carriers around the process tool bay at least in a vertical plane in front of one of said two rows of semiconductor process tools comprises at least one vehicle for receiving and delivering a wafer carrier to and from any one semiconductor process tool of said plurality of semiconductor process tools, and a vehicle guiding mechanism. The vehicle comprises a circular compartment structure including a plurality of compartments for buffering said wafer carrier between receiving it at a first location and delivering it at a second location. Each compartment is arranged for accommodating one wafer carrier. The compartment structure is rotatable around a symmetry axis of itself for an alignment. The distance between the two opposite rows of processing tools is determined so as to enable a displacement of at least one vehicle.

Wafer carrier transport system for tool bays

A semiconductor device on a wafer is formed by lithography with the following steps of: coating ( ) a lithography resist onto said wafer in a coating means ( ), exposing ( ) said wafer to an irradiation through a reticle in an exposure tool ( ), stabilizing ( ) said lithography resist for activating chemical reaction and developing said lithography resist in said predetermined areas in a developer means ( ) so as to reveal a predetermined lithography resist pattern on the wafer surface, stabilizing ( ) the lithography resist in a stabilization means ( ) for strengthening said pattern on the wafer surface, performing ( ) a metrology inspection of said lithography resist pattern on said wafer surface in a metrology tool ( ), etching, wet processing or implanting ions ( ) into said wafer in a processing cell ( ), wherein said metrology inspection is performed by atomic force microscopy in a atomic force microscopy module ( ) immediately after developing and baking said lithography resist adjacent to said stabilization means ( ).

Lithography method for forming semiconductor devices on a wafer utilizing atomic force microscopy

Growing community of inventors

Round Rock, TX, United States of America

Karl Emerson Mautz