Micron Technology Incorporated

Other

Seagate Technology Incorporated

Karl David Schuh

Kishore Kumar Muchherla

Jiangang Wu

Vamsi Pavan Rayaprolu

Sampath K Ratnam

Mustafa Nazmi Kaynak

Ashutosh Malshe

Sivagnanam Parthasarathy

Peter Sean Feeley

Xiangang Luo

Shane G Nowell

Devin M Batutis

Jeffrey S McNeil, Jr

Giuseppina Puzzilli

Byron D Harris

Daniel J Hubbard

Mark Ish

Abdelhakim Alhussien

Lyle E Adams

Niccolo' Righetti

Daniel A Boals

Pushpa Seetamraju

Dan Tupy

Harish Reddy Singidi

Gil Golov

Jung Sheng Hoei

Luca Bert

Gianni Stephen Alsasua

Renato Padilla, Jr

James Fitzpatrick

Shuhui Chen

Dheeraj Srinivasan

Qisong Lin

Ali Mohammadzadeh

William Richard Akin

Niccolo′ Righetti

Ayberk Ozturk

Amy Lee Wohlschlegel

Hong Lu

Guang Chang Ye

Boon Leong Yeap

Tommaso Vali

Aaron S Yip

Michele Piccardi

June Lee

Todd A Marquart

Umberto Siciliani

Yuriy Pavlenko

James P Crowley

Jeremy Isaac Nathaniel Werner

Tom V Geukens

Andrea Giovanni Xotta

Steven Gaskill

Rohitkumar Makhija

Jeffrey A Golden

Thad Omura

Aloysius C Ashley Wijeyeratnam

Sumit Puri

Guido Luciano Rizzo

Mastafa N Kaynak

Karl Huan-Yao Ko

Nathan Jared Hughes

Chris Hawkinson

Scott Ruple

Tom Volden

Exemplary methods, apparatuses, and systems include receiving a request to perform an operation in memory. A subdivision of the memory to which the request is directed is determined. A command completion time based upon a command type for the operation and which subdivision of the memory to which the request is directed is determined. A command is sent to the memory for the operation. A request is sent to the memory for a status of the command based upon the determined command completion time.

Adaptive command completion timers

A set of data items programmed to a first region of a memory subsystem is identified. The set of data items is programmed to the first region according to an initial sequence. A determination is made of whether the initial sequence corresponds to a target sequence associated with accessing the set of data items. Responsive to a determination that the initial sequence does not correspond to the target sequence, the set of data items is copied from the first region to a second region of the memory subsystem according to the target sequence.

Data reordering at a memory subsystem

A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.

Independent plane architecture in a memory device

A system includes a memory device and a processing device communicatively coupled to the memory device. The processing device is to write data to a number of groups of memory cells of the memory device in a physically non-contiguous manner. The processing device is further to track a sequence in which the number of groups of memory cells were written with the data. In response to a trigger event, the processing device is further to identify at least a portion of the number of groups of memory cells having data received over a predefined period preceding the trigger event based at least in part on the tracked sequence.

Memory sub-system write sequence track

A system includes a memory device and a processing device coupled to the memory device. The processing device can assign each of a plurality of superblocks to one of a plurality of groups. The processing device can monitor an order that each of the groups have been written to. The processing device can write data to a first block of a first superblock of a first of the plurality of groups.

Memory sub-system media management groups

A system includes a memory device including a plurality of groups of memory cells and a processing device that is operatively coupled to the memory device. The processing device is to receive a request to determine a reliability of the plurality of groups of memory cells. The processing device is further to perform, in response to receipt of the request, a scan operation on a sample portion of the plurality of groups of memory cells to determine a reliability of the sample portion that is representative of the reliability of the plurality of groups of memory cells.

Memory sub-system scan

Exemplary methods, apparatuses, and systems include allotting an initial amount of volatile memory to a write buffer. The write buffer stores batches of data to be written to non-volatile memory. In response to detecting a trigger to update the write buffer configuration, the volatile memory allotted to the write buffer is reduced.

Dynamic buffer limit for at-risk data

Exemplary methods, apparatuses, and systems include determining that a memory component to be subjected to a background data integrity scan does not currently satisfy an activity threshold. The background data integrity scan is delayed in response to determining memory component does not satisfy the activity threshold. In response to detecting a background data integrity scan trigger event, the background data integrity scan is performed.

Opportunistic background data integrity scans

A method includes initiating a voltage calibration scan with respect to a block of a memory device, wherein the block is assigned to a first bin associated with a first set of read voltage offsets, and wherein the first bin is designated as a current bin, measuring a value of a data state metric for the block based on a second set of read voltage offsets associated with a second bin having an index value higher than the first bin, determining whether the value is less than a current value of the data state metric measured based on the first set of read voltage offsets, and in response to determining that the value is less than the current value, designating the second bin as the current bin.

Voltage calibration scans to reduce memory device overhead

Method includes identifying, while programming sets of pages to dice of memory device, multiple sets of pages experiencing a variation in temporal voltage shift satisfying a threshold criterion; partitioning a set of pages of the multiple sets of pages into a set of fixed-length partitions; storing, in a metadata table, a value to indicate a size of each fixed-length partition; receiving a read operation directed at a page of the set of pages; determining, based on a logical block address of the read operation and on the value that indicates the size of each fixed-length partition, a partition of the set of fixed-length partitions to which the read operation corresponds; and searching within the metadata table to determine a block family to which the partition is assigned, wherein the searching is based on a first value associated with the set of pages and a second value associated with the partition.

Selective partitioning of sets of pages programmed to memory device

A set of host data items is received for programming to the memory subsystem. The set of host data items is programmed to a first region of the memory subsystem that includes one or more memory devices. A determination is made that a sequence at which the set of host data items are programmed across memory devices of the first region does not correspond to a target sequence associated with accessing the set of host data items via the first region. The target sequence corresponds to a sequence that enables a host data items programmed to the memory sub-system to be accessed in parallel. The set of host data items is copied from the first region to a second region of the memory subsystem. A sequence at which the set of host data items is copied to memory devices of the second region corresponds to the target sequence.

A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.

Managing voltage bin selection for blocks of a memory device

A system includes a memory device having multiple dice and a processing device operatively coupled to the memory device. The processing device receives a memory operation to program a set of pages of data across at least a subset of the plurality of dice. The processing device partitions the set of pages into a set of partitions and associates a first partition of the set of partitions with a first block family. The processing device assigns the first block family to a first threshold voltage offset bin and stores, in a metadata table, at least one bit to indicate that the set of pages is partitioned.

Managing workload of programming sets of pages to memory device

Exemplary methods, apparatuses, and systems include aggregating a plurality of memory status commands Each command of the plurality of memory status commands is assigned a corresponding bit on a memory interface. The plurality of memory status commands are sent in parallel as an aggregate status command to one or more memory components via the memory interface.

Memory status command aggregation

A system includes a memory device and a processing device coupled to the memory device. The processing device can determine a data rate from a first sensor and a data rate from a second sensor. The processing device can write a first set of data received from the first sensor at a first logical block address (LBA) in the memory device. The processing device can write a second set of data received from the second sensor and subsequent to the first set of data at a second LBA in the memory device. The processing device can remap the first LBA and the second LBA to be logically sequential LBAs. The second LBA can be associated with an offset from the first LBA and the offset can correspond to a data rate of the first sensor.

Memory sub-system logical block address remapping

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Santa Cruz, CA, United States of America

Karl David Schuh