USA as Represented by Secretary of the Navy

Intersil Corporation

Other

University of California

Northrop Grumman Systems Corporation

The Ohio State University

The Charles Stark Draper Laboratory, Inc.

Intersil Americas Inc.

University of Delaware

Karl D Hobart

Francis J Kub

Travis J Anderson

Andrew D Koehler

Marko J Tadjer

Tatyana I Feygelson

Michael Anthony Mastro

Eugene A Imhoff

Rachael L Myers-Ward

Mark Goorsky

John M Neilson

Joshua D Caldwell

Phillip E Thompson

Samuel Graham, Jr

Victor A Temple

Marc Steven Weinberg

Jonathan Jay Bernstein

Charles R Eddy, Jr

Eugene H Cook

Virginia D Wheeler

Bradford B Pate

Henry F Gray

Jonathan L Shaw

Bernard F Phlips

Alan G Jacobs

Mark E Twigg

Robert E Stahlbush

Roger Lake

Asif Khan

Eric A Wulf

Mona A Ebrish

Sean L Rommel

Zhe Cheng

Geoffrey M Foster

Luke Yates

Tingyu Bai

Yekan Wang

Lunet E Luna

Jordan D Greenlee

Mario Ancona

Paul Berger

Vincent Gambin

Orest J Glembocki

Ioulia Smorchkova

Jennifer K Hite

James E Butler

Boris N Feygelson

James C Gallagher

Nadeemullah A Mahadik

Yuhao Zhang

Gregory Todd Lewis

Matthew Porter

Daniel G Georgiev

Paul R Berger

Rajinder S Sandhu

Joseph A Spencer

Raghav Khanna

Tolen Michael Nelson

Prakash Pandey

Michael Robert Hontz

Eugene I Imhoff

Mike Spencer

Francis Kud

Robert H Esser

Kendrick X Liu

Jeff McKay

David Shahin

A self-aligned lithography process for the fabrication of an electronic device having predefined areas of a second semiconductor material having a second conductivity type deposited into trenches formed in a first semiconductor material layer having a first conductivity type. A single lithography mask is used for etching trenches in the first semiconductor material, enabling cleaning of the trenches, and providing defined areas for the deposition of the second semiconductor material into the first semiconductor material. The presence of the areas of the second semiconductor material within the first semiconductor material creates a heterojunction beneath a metal for the formation of a first type of contact to the first semiconductor material and a second type of contact to the second type of material. By using a single mask for the etching, cleaning, and filling steps, misalignment issues plaguing devices having small (1-2 μm) feature sizes is eliminated.

β-GaOjunction barrier Schottky (JBS) diodes with sputtered p-type NiO

A technique for selective-area diffusion doping of III-N epitaxial material layers and for fabricating power device structures utilizing this technique. Dopant species such as Mg are introduced into the III-N material layer and are diffused into the III-N material by annealing under stable or metastable conditions. The dopant species can be introduced via deposition of a metal or alloy layer containing such species using sputtering, e-beam evaporation or other technique known to those skilled in the art. The dopant material layer is capped with a thermally stable layer to prevent decomposition and out-diffusion, and then is annealed under stable or metastable conditions to diffuse the dopant into the III-N material GaN without decomposing the surface.

Selective area diffusion doping of III-N materials

Semiconductor heterostructures having an engineered polarization. Semiconductor materials having specified crystallographic directions and specified polarizations are directly bonded to one another by means of atomic layer bonding without the use of any interfacial bonding materials, where spontaneous polarization of the two layers produced by joining the two materials by direct wafer bonding produces a strong 2DEG or 2DHG at the interface. Embodiments include GaN/AlN and AlN/GaN heterostructures having an N- or Ga-polar GaN layer directly bonded to an N- or Al-polar Al layer. Other embodiments can incorporate an InN epitaxial layer or an alloy incorporating an N-polar, Al-polar, or Ga-polar material having In, Al, or Ga in the crystal lattice, e.g., (InAlN), InGaN, AlGaN, InAlGaN, where (0<x≤1, 0<y≤1, 0<x+y≤1).

Polarization-engineered heterogeneous semiconductor heterostructures

A hybrid edge termination structure and method of forming the same. The hybrid edge termination structure in accordance with the invention is based on a junction termination extension (JTE) architecture, but includes an additional Layer of guard ring (GR) structures to further implement the implantation of dopants into the structure. The hybrid edge termination structure of the invention has a three-Layer structure, with a top Layer and a bottom Layer each having a constant dopant concentration in the lateral direction, and a middle Layer consisting of a plurality of spatially defined alternating regions that exhibit the electrical properties of either the top or bottom layer. By including the second layer, a discretized varying charge profile can be obtained that approximates the varying charge profile obtained using tapered edge termination but with easier manufacturing and lower cost.

Multi-layer hybrid edge termination for III-N power devices

A light controlled semiconductor switch (LCSS), method of making, and method of using are provided. In embodiments, a vertical LCSS includes: a semiconductor body including a photoactive layer of gallium nitride (GaN) doped with carbon; a first electrode in contact with a first surface of the semiconductor body, the first electrode defining an area through which light energy from at least one light source can impinge on the first surface; and a second electrode in contact with a second surface of the semiconductor body opposed to the first surface, wherein the vertical LCSS is configured to switch from a non-conductive off-state to a conductive on-state when the light energy impinging on the semiconductor body is sufficient to raise electrons within the photoactive layer into a conduction band of the photoactive layer.

Low resistance photoconductive semiconductor switch (PCSS)

Methods for obtaining a free-standing thick (>5 μm) epitaxial material layer or heterostructure stack and for transferring the thick epitaxial layer or stack to an arbitrary substrate. A thick epitaxial layer or heterostructure stack is formed on an engineered substrate, with a sacrificial layer disposed between the epitaxial layer and the engineered substrate. When the sacrificial layer is removed, the epitaxial layer becomes a thick freestanding layer that can be transferred to an arbitrary substrate, with the remaining engineered substrate being reusable for subsequent material layer growth. In an exemplary case, the material layer is a GaN layer and can be selectively bonded to an arbitrary substrate to selectively produce a Ga-polar or an N-polar GaN layer.

Transferring large-area group III-nitride semiconductor material and devices to arbitrary substrates

Light controlled switching modules are provide. In embodiments, a light controlled switching module includes: a housing; a light controlled semiconductor switch mounted to the housing, the light controlled semiconductor switch including a semiconductor body; at least one light source mounted to the housing in a spaced relationship from the light controlled semiconductor switch and positioned to direct light emitted from the at least one light source toward the semiconductor body; and first and second electrodes mounted to the housing and connected to the light controlled semiconductor switch, wherein the first and second electrodes are configured to have variable resistance between the first and the second electrode.

Light controlled switch module

A method of fabricating suspended beam silicon carbide microelectromechanical (MEMS) structure with low capacitance and good thermal expansion match. A suspended material structure is attached to an anchor material structure that is direct wafer bonded to a substrate. The anchor material structure and the suspended material structure are formed from either a hexagonal single-crystal SiC material, and the anchor material structure is bonded to the substrate while the suspended material structure does not have to be attached to the substrate. The substrate may be a semi-insulating or insulating SiC substrate. The substrate may have an etched recess region on the substrate first surface to facilitate the formation of the movable suspended material structures. The substrate may have patterned electrical electrodes on the substrate first surface, within recesses etched into the substrate.

Silicon carbide structure, device, and method

A method for growing polycrystalline diamond films having engineered grain growth and microstructure. Grain growth of a polycrystalline diamond film on a substrate is manipulated by growing the diamond on a nanopatterned substrate having features on the order of the initial grain size of the diamond film. By growing the diamond on such nanopatterned substrates, the crystal texture of a polycrystalline diamond film can be engineered to favor the preferred &#x3c;110&#x3e; orientation texture, which in turn enhances the thermal conductivity of the diamond film.

Diamond on nanopatterned substrate

A method for mapping and analyzing a GaN substrate to identify areas of the substrate suitable for fabrication of electronic devices thereon. Raman spectroscopy is performed over the surface of a GaN substrate to produce maps of the Eand Apeaks at a plurality of areas on the substrate surface, the Eand Apeaks being associated with known concentrations of defects and charge carriers, so that areas of the GaN substrate having relatively high resistivity or conductivity which make those areas suitable or unsuitable for fabrication of electronic devices can be identified. The devices can then be fabricated only on suitable areas of the substrate, or the size of the devices can be tailored to maximize the yield of devices fabricated thereon. Substrates not meeting a threshold level of defect and/or charge carrier concentration can be discarded without fabrication of poor-quality devices thereon.

Mapping and evaluating GaN wafers for vertical device applications

Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide.

Heterojunction devices and methods for fabricating the same

A high electron mobility transistor (HEMT) and method of producing the same are provided. The HEMT includes a barrier layer formed on a GaN layer. The HEMT also includes a ZrOgate dielectric layer formed by either a ZTB precursor, a TDMA-Zr precursor, or both. The HEMT may also include a recess in the barrier layer in the gate region of the HEMT. The HEMTs may operate in an enhancement mode.

High electron mobility transistors and methods for fabricating the same

A method of cleaving includes providing a substrate. Optionally, the substrate includes &#x3b2;-gallium oxide, hexagonal zinc sulfide, or magnesium selenide. The substrate includes at least one natural cleave plane and a crystallinity. The substrate is cleaved along a first natural cleave plane of the at least one natural cleave plane. The cleaving the substrate along the first natural cleave plane includes the following. A micro-crack is generated in the substrate while maintaining the crystallinity adjacent to the micro-crack by generating a plurality of phonons in the substrate, the micro-crack comprising a micro-crack direction along the first natural cleave plane. The micro-crack is propagated along the first natural cleave plane while maintaining the crystallinity adjacent to the micro-crack. Optionally, generating a micro-crack in the substrate by generating a plurality of phonons in the substrate includes generating the plurality of phonons by electron-hole recombination. Optionally, the electron-hole recombination includes non-radiative electron-hole recombination.

UV laser slicing of &#x3b2;-GaOby micro-crack generation and propagation

Growing community of inventors

Alexandria, VA, United States of America

Karl D Hobart