Synopsys, Inc.

Karim El Sayed

Victor Moroz

Xi-Wei Lin

Terry Sylvan Kam-Chiu Ma

Qiang Lu

Zudian Qin

Disclosed is technology for evaluating the performance of various conducting structures in an integrated circuit. A three-dimensional circuit representation of a circuit design is provided. The three-dimensional circuit representation includes a plurality of conducting structures including a first conducting structure which has a length L. A plurality of longitudinally adjacent volume elements is identified in the conducting structure. A width Wand a height Hare estimated for each volume element n in the conducting structure. Furthermore, the local resistivity &#x3c1;for each volume element n is estimated based on a function that is dependent upon the length L of the conducting structure and the width Wand height Hof the volume element n. The resistance of a conducting structure is estimated in dependence upon the resistivity &#x3c1;for each of the volume elements n in the plurality of volume elements in the conducting structure.

Computationally efficient nano-scale conductor resistance model

Disclosed is technology for evaluating the performance, power, area, and cost of a new or significantly modified IC fabrication process. A layout of a circuit design is provided, the circuit design including pins, transistors, and interconnects. The interconnects have at least two endpoints, each of the endpoints being either a terminal of a transistor or a pin in the circuit design. The locations for a plurality of transistor and interconnect endpoints in the layout are identified. A three-dimensional circuit representation is fabricated in accordance with the layout and the fabrication process. Parasitic resistance and capacitance values are estimated for pairs of interconnect endpoints which share an interconnect in the three-dimensional circuit representation. An annotated netlist is developed for the plurality of the transistors interconnects endpoints identified from the layout, and which further indicates the parasitic resistance values and parasitic capacitance values estimated from the three-dimensional circuit representation.

Automated resistance and capacitance extraction and netlist generation of logic cells

Roughly described, a method for developing a set of design rules for a fabrication process in development includes, for each of several candidate DRUTs for the fabrication process, laying our a logic cell based on the DRUT, the logic cell having at least one transistor and at least one interconnect, simulating fabrication of the logic cell according to the fabrication process and the layout, simulating behavior of the logic cell structure, including characterizing the combined behavior of both the first transistor and the first interconnect, evaluating performance of the logic cell structure in dependence upon the behavior as characterized, and recording in a database, in association with an indication of the DRUT, values indicating performance of the logic cell. The database can be used to select the best DRUT for the fabrication process.

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Santa Clara, CA, United States of America

Karim El Sayed