Qualcomm Incorporated

Silanna Asia Pte Ltd

Appulse Power Inc.

Atlazo, Inc.

Karim Arabi

Wenqing Wu

Kendrick Hoy Leong Yuen

Evgeni Petrovich Gousev

Volodimir Slobodyanyuk

Aleksandar Radic

Seyed-Behzad Mahdavikhah-Mehrabad

Matthew Stuart Grob

Ravindra Vaman Shenoy

Mete Erturk

Raghu Sagar Madala

Sheikh Mohammad Ahsanuzzaman

Rajamani Sethuram

Yang Du

Rajesh K Pankaj

John Michael Wyrwas

Sajith Balraj

Javid Jaffari

Michael Laisne

Hongmei Liao

Rodolfo Beraha

Mamta Bansal

Tsvetomir Petrov

Yaojun Zhang

Khusro Sajid

Aspects of the disclosure are related to a Lidar device, comprising: a vibrating fiber optic cantilever system on a transmit (TX) path; and a two-dimensional (2D) light sensor array on a receive (RX) path.

Implementation of the focal plane 2D APD array for hyperion Lidar system

Disclosed are methods, apparatus and systems for a binary neural network accelerator engine. One example circuit is designed to perform a multiply-and-accumulate (MAC) operation using logic circuits that include a first set of exclusive nor (XNOR) gates to generate a product vector based on a bit-wise XNOR operation two vectors. The result is folded and operated on by another set of logic circuits that provide an output for a series of adder circuits. The MAC circuit can be implemented as part of binary neural network at a small footprint to effect power and cost savings.

Binary neural network accelerator engine methods and systems

A power adapter for supplying electrical power to a device includes a processor, an interface for power transfer with the device, a multi-winding feedback converter to receive an AC power input and to convert the AC power input to a DC power output over the interface for the device, and a power conversion control circuit. A voltage level of the DC power output is set based on a reference voltage produced by the processor. The power conversion control circuit receives the reference voltage and a control signal based on the voltage level of the DC power output to generate switch control signals to control switches of the multi-winding feedback converter to control the voltage level of the DC power output. The processor recognizes a load associated with the device and sets, using the reference voltage, the DC power output based on the recognized load.

AC/DC power adapter with multi-winding feedback converter

A power adapter for supplying electrical power to a mobile device. The power adapter may have a processor and an interface for data communication and power transmission with the mobile device, memory internal to a casing of the power adapter, and an AC/DC power conversion circuit electrically coupled to the processor. The AC/DC power conversion circuit is configured to receive an AC power input and convert the AC power input to a DC power output over the interface for the mobile device. The processor is configured to: recognize a load associated with the mobile device connected to the DC power output; set the DC power output based on the load; receive backup data from the mobile device over the interface; and store the backup data from the mobile device within the memory.

AC/DC power adapter with accessible internal memory

Disclosed herein are techniques for light beam scanning in a light detection and ranging (LIDAR) system. The LIDAR system includes a beam shaping subsystem configured to generate an illumination pattern elongated in a first direction, and a scanning subsystem configured to direct the elongated illumination pattern towards a plurality of positions along a second direction different from the first direction. The LIDAR system further includes a sensor configured to generate a detection signal in response to detecting light reflected by a target object illuminated by the elongated illumination pattern, and a processor configured to determine a characteristic of the target object based on the detection signal.

Hybrid scanning lidar systems

Implementation of the focal plane 2D APD array for hyperion lidar system

A light detection and ranging (LIDAR) apparatus includes dual beam scanners with dual beam steering. A first beam scanner in the LIDAR apparatus scans a wider area in one or more of a first plurality of scan patterns, and a second beam scanner in the LIDAR apparatus scans a narrower area in one or more of a second plurality of scan patterns different from the first plurality of scan patterns.

Light detection and ranging (LIDAR) system with dual beam steering

Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.

Integrated circuit leakage power reduction using enhanced gated-Q scan techniques

Systems and methods are directed to a three-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure, with a first GSHE-MTJ and a second GSHE-MTJ coupled between a first combined terminal and a second combined terminal, and a slave stage formed from a first inverter cross-coupled with a second inverter. A first data value is read out from the slave stage during a read phase of the same clock cycle that a second data value is written into the master stage during a write phase. The three-phase NVFF includes three control signals, for controlling an initialization phase of the slave stage, the read phase, and the write phase.

Three-phase GSHE-MTJ non-volatile flip-flop

Methods for constructing three dimensional integrated circuits and related systems are disclosed. In one aspect, a first tier is constructed by creating active elements such as transistors on a holding substrate. An interconnection metal layer is created above the active elements. Metal bonding pads are created within the interconnection metal layer. A second tier is also created, either concurrently or sequentially. The second tier is created in much the same manner as the first tier and is then placed on the first tier, such that the respective metal bonding pads align and are bonded one tier to the other. The holding substrate of the second tier is then released. A back side of the second tier is then thinned, such that the back surfaces of the active elements (for example, a back of a gate in a transistor) are exposed. Additional tiers may be added if desired essentially repeating this process.

Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems

Systems and methods are directed to a memory element comprising a hybrid giant spin Hall effect (GSHE)-spin transfer torque (STT) magnetoresistive random access memory (MRAM) element, which includes a GSHE strip formed between a first terminal (A) and a second terminal (B), and a magnetic tunnel junction (MTJ), with a free layer of the MTJ interfacing the GSHE strip, and a fixed layer of the MTJ coupled to a third terminal (C). The orientation of the easy axis of the free layer is perpendicular to the magnetization created by electrons traversing the GSHE strip between the first terminal and the second terminal, such that the free layer of the MTJ is configured to switch based on a first charge current injected from/to the first terminal to/from the second terminal and a second charge current injected/extracted through the third terminal into/out of the MTJ via the third terminal (C).

High density low power GSHE-STT MRAM

Systems and methods pertain to avoiding undesirable current paths or sneak paths in spintronic logic gates formed from Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) elements. Sneak path prevention logic is coupled to the GSHE MTJ elements, to prevent the sneak paths. The sneak path prevention logic may include one or more transistors coupled to the one or more GSHE MTJ elements, to restrict write current from flowing from an intended pipeline stage to an unintended pipeline stage during a write operation. The sneak path prevention logic may also include one or more diodes coupled to the one or more GSHE MTJ elements to prevent a preset current from flowing into input circuitry or a charge current generation circuit. A preset line may be coupled to the one or more GSHE MTJ elements to divert preset current from flowing into unintended paths.

Elimination of undesirable current paths in GSHE-MTJ based circuits

Systems and methods are directed to a single-phase non-volatile flip-flop (NVFF), which includes a master stage formed from a dual giant spin Hall effect (GSHE)-magnetic tunnel junction (MTJ) structure, the dual GSHE-MTJ structure comprising a first GSHE-MTJ and a second GSHE-MTJ coupled between a first combined terminal and a second combined terminal, and a slave stage formed from a first inverter coupled to a second inverter. During a single clock cycle of a clock, a first data value is read out from the slave stage when a clock is in a high state and a second data value is written into the master stage, when the clock is in a low state. The first and second inverters are cross coupled in a latch configuration to hold the first data value as an output, when the clock is in the low state.

Single phase GSHE-MTJ non-volatile flip-flop

A method includes identifying at least a portion of a design of a semiconductor device to be fabricated as a yield sensitive circuit. The method also includes, in response to identifying the yield sensitive circuit, forming a scan chain. Forming the scan chain includes inserting the yield sensitive circuit between a pair of flip flops and connecting the yield sensitive circuit to the pair of flip flops.

Growing community of inventors

San Diego, CA, United States of America

Karim Arabi