Nokia Mobile Phones Limited

Nokia Corporation

Kari Halonen

Saska J Lindfors

Pekka Kostiainen

Marko Kosunen

Ari Paasio

Asko Kananen

Aarno P&auml;rssinen

Tuomas Huikko

The present invention proposes a multiplier device performing multiplication of different powers of two serially in time (not in parallel) in order to further reduce the area needed for a hardware realization. By virtue thereof, it is enabled to use only one adder in connection with the multiplication which contributes to a reduced hardware amount and reduced required area for the hardware. A shifter means based on binary weighted shifting is used for shifting in connection with the multiplication, thereby reducing the required hardware amount (number of multiplexers and hardwired shifting elements) and thus reducing the area for hardware implementation still further. The present invention can be used in applications using digital multiplication, such as in digital signal processing DSP, digital filters and/or finite impulse response filters FIR filters as well as programmable and/or adaptive digital filters. As the multiplier is represented in CSD coding, the number of necessary shifting operations can be reduced and the number of necessary additions can be reduced, thus contributing to a reduced area needed for a hardware realization of a shifting means and a multiplier device on a silicon chip.

Multiplier and shift device using signed digit representation

The invention pertains to a method and corrector (IC ) for correcting an error in a parallel analog-to-digital conversion. Such a correctable error is caused by uncertainties in the reading of the states of parallel comparing elements (IC IC IC IC ) in the converter, said uncertainties being brought about by nonideality, such as non-simultaneous state latching. This error is corrected using a nonlinear cellular neural network preferably such that the real level of the phenomenon compared by means of comparing elements (IC IC IC IC ) is estimated by estimating the states corresponding to correct reading of the comparing elements (IC IC IC IC ) read temporally or otherwise erroneously.

Method for correcting errors in parallel A/D conversion, corrector and parallel A/D converter

Method and circuit for sampling a signal at high sampling frequency

An IC multiplier circuit has four cells having bipolar transistors to give an exponential input-output function. Each cell has a squaring bipolar transistor and an emitter follower. Differential output signals are taken from the squaring bipolar transistor. The voltage follower is an emitter follower with the bias current through it is substantially larger, e.g. about 10 times larger, than the bias current through the squaring bipolar transistor, which has an emitter resistor.

Integrated multiplier circuit

A delta-sigma modulator for converting an analog input signal into a digital output signal comprises a modulator input (,) and a first analog to digital converter (,) coupled to the modulator input (,). The first analog to digital converter has a first analog input and a first digital output. The delta-sigma modulator further comprises an error quantization unit (,) coupled to the first digital output for determining the quantization error caused by the first analog to digital converter (,). Additionally it comprises first signal combining means (,) for combining the outputs of the first analog to digital converter and said error quantization unit to form the digital output signal.

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Helsinki, Finland

Kari Halonen