International Business Machines Corporation

Karen E Yokum

John Andrew Schumann

Debapriya Chatterjee

Bryant Cockcroft

Kevin Barnett

Paul Umbarger

Shakti Kapoor

Larry Scott Leitner

Tharunachalam Pindicura

Lawrence Leitner

Paul Frank Lecocq

Vivek Britto

Jeffrey W Kellington

Lance G Hehenberger

Jamory Hawkins

John Charles Goss

Rahul Batra

Christopher R Jones

Christopher M Riedl

Omesh Bajaj

Shricharan Srivatsan

Aishwarya Dhandapani

Yan Xia

Grace Y Liu

Piriya K Hall

Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for detecting deviations from targeted design performance in accelerator/emulator environment. In an embodiment, the method comprises loading target vales for a performance metric onto a hardware-accelerated simulator; setting breakpoints to pause the simulator at defined intervals; simulating, by the hardware-accelerated simulator, execution of a circuit design. The method further comprises during the simulating, using said breakpoints to pause the simulating at the defined intervals, and during each pause, comparing a measured value for the performance metric to the target value for the performance metric; and ending the simulation when a specified condition based on said comparing is met. In embodiments, when a difference between the measured value for the performance metric and the target value for the performance metric is within a preset tolerance, the pause is ended and the simulation continues.

Detecting deviations from targeted design performance in accelerator/emulator environment

A hardware request of an application is detected. The Application executes on a virtualized computer system. It is determined that the hardware request includes a counter. The counter is to be performed by the virtualized computer system. The counter includes a counter value. The hardware request is intercepted before the it is processed by a hypervisor that hosts the virtualized computer system. The interception is based on the determining the hardware request includes the counter. The counter value is saved in a secure memory. The secure memory is obscured from the hypervisor. A scrambled counter value is generated. The hardware request is updated with the scrambled counter value. After the hardware request is updated it is provided to the hypervisor.

Obscuring information in virtualization environment

Provided are systems, methods, and media for handling simulation of logic under test. An example method includes receiving a simulation model for the logic under test. Generating second logic that is configured to create a set of output logic signals based on an existing set of input logic signals of the logic under test. Rebuilding the simulation model based, at least in part, on the second logic. Examining a netlist of the rebuilt simulation model to identify the set of output logic signals created by the second logic. Generating during the execution of the simulation, a bus trace that is configured to capture at least the identified set of output logic signals.

Generating and adding additional control information to logic under test to facilitate debugging and comprehension of a simulation

A method of checking for a stall condition in a processor is disclosed, the method including inserting an inline instruction sequence into a thread, the inline instruction sequence configured to read the result from a timing register during processing of a first instruction and store the result in a first general purpose register, wherein the timing register functions as a timer for the processor; and read the results from the timing register during processing of a second instruction and store the results in a second general purpose register, wherein the second instruction is the next consecutive instruction after the first instruction. The inline thread sequence may be inserted in sequence with the thread and further configured to compare the difference between the result in the first and second general purpose register to a programmable threshold.

Method and system for detection of thread stall

A processor includes a performance monitor that logs reservation losses, and additionally logs reasons for the reservation losses. By logging reasons for the reservation losses, the performance monitor provides data that can be used to determine whether the reservation losses were due to valid programming, such as two threads competing for the same lock, or whether the reservation losses were due to bad programming. When the reservation losses are due to bad programming, the information can be used to improve the programming to obtain better performance.

Processor performance monitor that logs reasons for reservation loss

A method and an information handling system having a plurality of processors connected by a cross-processor network, where each of the plurality of processors preferably has a filter construct having an outgoing filter list that identifies logical partition identifications (LPIDs) that are exclusively assigned to that processor and/or an incoming filter list that identifies LPIDs on that processor and at least one additional processor in the system. In operation, if the LPID of the outgoing translation invalidation instruction is on the outgoing filter list, the address translation invalidation instruction is acknowledged on behalf of the system. If the LPID of the incoming invalidation instruction does not match any LPID on the incoming filter list, then the translation invalidation instruction is acknowledged, and if the LPID of the incoming invalidation instruction matches any LPID on the incoming filter list, then the invalidation instruction is sent into the respective processor.

Address translation cache invalidation in a microprocessor

An instruction may be associated with a memory address. During execution of the instruction, the memory address may be translated to a next level memory address. The instruction may also be marked for address tracing. If the instruction is marked for address tracing, then during execution of the instruction, the memory address and the next level memory address may be recorded.

Identifying translation errors

A system and method including a processor configured to, based on encountering an instruction that does not modify the architectural state of the processor, preferably a prefetch instruction, that is being executed by the processor, determine whether utilization of a first queue used in processing the instruction is over a first queue utilization limit; in response to the first queue utilization being over the first queue utilization limit, do not execute the prefetch instruction; and in response to the first queue utilization being under the first queue utilization limit, at least partially process the prefetch instruction.

Dynamic modification of instructions that do not modify the architectural state of a processor

A method, computer program product, and computer system are disclosed that in one or more embodiments includes issuing, from an issuing processor in the computer system, an address translation invalidation instruction with a return marker, wherein the address translation invalidation instruction is to invalidate one or more address translation entries in one or more storage locations in the computer system and wherein the return marker comprises an instruction to return information to the issuing processor indicating the identity of each processor where an invalidated entry was located. The method, product, and system in an embodiment further includes broadcasting the address translation invalidation instruction with the return marker to one or more storage locations of one or more of the processors in the computer system other than the issuing processor; invalidating the address translation entry corresponding to the broadcasted address translation invalidation instruction; and returning to the issuing processor information on each storage location corresponding to the invalidated address translation entry. In one or more embodiments, the returned information is used to determine the performance of the computing system, identifying the storage locations where data was located.

System and method including broadcasting an address translation invalidation instruction with a return marker to indentify the location of data in a computing system having mutiple processors

A computer system includes a hardware accelerator and host processor. The hardware accelerator executes a simulation of a first logical model according to a plurality of simulation cycles. The host processor determines a fault checkpoint based on a logic fault that occurs in response to executing the simulation. The host processor verifies removal of the logic fault based on rerunning the simulation from the fault checkpoint.

Precise verification of a logic problem on a simulation accelerator

Embodiments of the present disclosure provide a method, a system, and a computer readable storage medium for circuit design verification. The user generates a breakpoint by execution of test bench code. A callback function is registered at an application level associated with the breakpoint. The callback function is configured to execute in response to an occurrence of the associated breakpoint at the system level. A hardware-accelerated simulator simulates an execution of a circuit design using the test bench code. In response to triggering the breakpoint at the system level, the execution of the circuit design at the system level is paused and the callback function associated with the breakpoint at the application level is executed.

Circuit design verification in a hardware accelerated simulation environment using breakpoints

An apparatus and a method are disclosed for tracking use of a specialized hardware component in symmetric multiprocessing computing device. A device includes a memory and one or more multi-core processors attached to a coherent memory bus. A proxy for a specialized hardware component (SHC) such as an accelerator, FPGA, or ASIC is placed in communication with the coherent memory bus. The proxy may be attached to another bus such as a peripheral component interconnect express (PCIe) bus. A tracker updates an allocated counting register with counts of events related to use of the SHC. When requested, information from the counting register is provided such as to an external device or client communicating with the multiprocessing computing device. The tracker may follow calls or messages to the SHC. The tracker may accumulate a count of message size or mode of use or use of certain functions of the SHC.

Growing community of inventors

Austin, TX, United States of America

Karen E Yokum