Altera Corporation

Kar Keng Chua

Boon Jin Ang

Kok Heng Choe

Hee Kong Phoon

Sammy S Cheung

Edwin Yew Fatt Kok

Kim Pin Tan

Chooi Pei Lim

Thow Pang Chong

Wei Lian Goay

Jun Pin Tan

Joo Ming Too

Jinyong Yuan

Chuan Khye Chai

Ji Park

Yee Liang Tan

Kok Yoong Foo

Yew Fatt Kok

Tze Swan Tan

Jayabrata Ghosh Dastidar

Choong Kit Wong

Eng Huat Lee

Tat Mun Lui

Siang Poh Loh

Siew Ling Yeoh

Ie Chen Chia

Geok Sun Chong

Chiew Khiang Kuit

Kian Chin Yap

Yew Fatt (Edwin) Kok

Sze Huey Soo

Evgenii Puchkaryov

Yan Jiong Boo

Phooi Choong Loh

Kok Sun Chia

Kam Fai Suit

Clock distribution circuitry for a structured ASIC device includes a deterministic portion and configurable portions. The deterministic portion employs a predetermined arrangement of conductor segments and buffers for distributing a clock signal to a plurality of predetermined locations on the device. From each predetermined location, an associated configurable portion of the clock distribution circuitry distributes the clock signal to any clock utilization circuitry needing that clock signal in a predetermined area of the structured ASIC that is served from that predetermined location.

Clock signal networks for structured ASIC devices

Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements ('HLEs'), each of which can provide a portion of the full functionality of an FPGA logic element ('LE'). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

Application-specific integrated circuit equivalents of programmable logic and associated methods

Integrated circuit packages with a signal routing control through a given direction are disclosed. A disclosed integrated circuit package includes a plurality of interconnects. A first logic circuitry of a first integrated circuit may produce a first signal that may be transmitted to a second integrated circuit. The integrated circuit package further includes interconnect circuitry disposed between the first and second integrated circuits. Multiplexing circuitry may select the first signal from second logic circuitry when the first logic circuitry is defective and may direct the signal as output signal to the second integrated circuit through a given interconnect.

Method and apparatus for providing signal routing control

Methods, computer program products, and systems are disclosed associated with calculating a routability metric for a second IC design using inputs from the compilation to a first IC design. The first and second IC designs are alternative implementation options for a user circuit design, such as FPGA and structured ASIC options. Information about user design demands on routing resources of one IC design are considered along with information about the projected supply of routing resources in another IC design, to produce a routing metric. The routing metric may be mapped to a degree of difficulty indicator, and either may be used to condition a compile of the user circuit to the second IC design or be used in other ways.

Predicting routability of integrated circuits

Circuits for a multiplier with a built-in accumulator and a method of performing multiplication with accumulation are disclosed. An embodiment of the disclosed circuits includes a logic circuit coupled to receive two inputs. The logic circuit is capable of generating a plurality of value bits from the inputs received. In one embodiment, the logic circuit includes a Booth recoder circuit that generates a plurality of partial products. A block of adders is coupled to logic circuit to receive and sum up the value bits. An adder adds the summation result from the block of adders to a previous accumulated value to generate intermediate sum and carry values. An accumulator, coupled to the adder, receives and stores the intermediate values.

Multiplier with built-in accumulator

A method to modify a first IC design into a second IC design, the first and second IC designs specifying a common interconnection layer with a plurality of interconnections, is disclosed. The method includes identifying an interconnection from plurality of interconnections within the common interconnection layer. The interconnection is unused for routing signals in the first IC design. The metal layer that is coupled with the identified interconnection is removed from the first IC design to generate a modified design. The identified interconnection of the first IC design is placed into one of an invisible state or a temporarily removed state in the modified design. The metal layer in the modified design is routed for a specific logic gate design. The modified design is then stored as the second IC design.

Method to modify an integrated circuit (IC) design

Integrated circuits (ICs) with configurable test pins and a method of testing an IC are disclosed. An IC has input/output (I/O) pins that can be configured either as a test input pin, a test output pin or a user I/O pin. Selector circuits are used to selectively route and couple the I/O pins to various logic blocks and test circuitry on the IC. Selector circuits are also used to selectively couple either a user output or a test output to different I/O pins on the IC. Switches are used to configure the selector circuits and route test signals within the IC. Different configurations of the switches determine how the signals are routed. Test input signals from an I/O pin may be routed to any test circuitry within the IC and test output signals from a test circuit may be routed to any I/O pin on the IC.

Integrated circuit with configurable test pins

Memory performance in programmable logic is significantly increased by adjusting circuitry operation to adjust for variations in process, voltage, or temperature. A calibration circuit adjusts control signal timing, dynamically and automatically, to compensate real time to process, voltage, and temperature variation. A feedback system using a control block and a dummy mimicking concept are provided.

Real time feedback compensation of programmable logic memory

Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.

Data encoding scheme to reduce sense current

A method of designing at IC is described. In one embodiment, the method includes providing an option to select a mask layer set from a plurality of mask layer sets, the plurality of mask layer sets including a first mask layer set and a second mask layer set, where the second mask layer set is an alternative mask layer option to the first mask layer set. In one embodiment, the method further includes receiving a selection from a user choosing a mask layer set from the plurality of mask layer sets. In one embodiment, the receiving occurs after design of the IC and prior to fabrication of the IC. Also, in one embodiment, the plurality of mask layer sets are predetermined mask layer sets. In one embodiment, the first mask layer set is a standard threshold voltage (SVT) mask layer set and the second mask layer set is a high threshold voltage (HVT) mask layer set. In one embodiment, core devices of the SVT mask layer set are SVT devices and some periphery devices of the SVT mask layer set are HVT devices. In one embodiment, hybrid cell (H-cell) devices of the HVT mask layer set are HVT devices and some periphery devices of the HVT mask layer set are HVT devices.

Method of designing integrated circuits including providing an option to select a mask layer set

A circuit includes a receiver channel and a built-in self-test circuit. The receiver channel has a serializer and a deserializer. The built-in self-test circuit generates test signals that are transmitted in parallel to the serializer during a test of the receiver channel. The serializer converts the test signals into serial test signals. The deserializer converts the serial test signals into parallel test signals that are transmitted to the built-in self-test circuit.

Techniques for performing built-in self-test of receiver channel having a serializer

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Penang, Malaysia

Kar Keng Chua