Intel Corporation

Kapila B Udawatta

Anthony Babella

David W Grawrock

Bruce Querbach

Tieyu Zheng

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Vui Yong Liew

Hermann Gartler

Ashok N Kabadi

Samie B Samaan

Keith A Drescher

Mukesh Kataria

Jay Joseph Nejedlo

Lyle E Cool

Razi Uddin

Russell J Wunderlich

James J Grealish

Brian Meyer

Abhijit Davare

Priyadarsan Patra

William Penner

Ridvan A Sahan

Rahima K Mohammed

Wee Hoo Cheah

Arun R Ramadorai

Yuen Tat Lee

John L Baudrexl

Loren James McConnell

Kip C Killpack

Kyle Markley

Christian E Iovin

Padmakumar Gopal

Travis K Goff

Sanjay S Salem

Evan J Halprin

David C Florey

Jiun Long Foo

Selvakumar Raja Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

An apparatus with a generator to generate a pattern and multiple scan chains configured to receive the pattern from the generator. Multiple signature registers coupled to the scan chains, to receive an output of at least one of scan chains during a mode of the integrated device.

Method and apparatus for fault tolerant and flexible test signature generator

A circuit to analyze or test a first or second logic coupled to an input/output circuit by storing a plurality of signals into a plurality of flip flops. The flip flops store the plurality of signals for a first mode of operation to observe at least one node within the first logic. Also, the flip flops load data values in response to control logic for a second mode of operation to control at least one node within the second logic.

Method and apparatus to enhance testability of logic coupled to IO buffers

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Folsom, CA, United States of America

Kapila B Udawatta