Allegro Microsystems, LLC

Murata Manufacturing Co., Ltd.

Kapil Kesarwani

Mackenzie Tope

David J Perreault

Yevgeniy A Tkachenko

Aaron Cook

John R Hoversten

A circuit comprising a first capacitor configured to be charged to a voltage representing state information of a compensator, a second capacitor, a buffer circuit configured to charge the second capacitor to a voltage substantially equal to that of the first capacitor and a switching network configured to transition between a first state and a second state. When the switching network is in the first state, the second capacitor is charged to the voltage across the first capacitor. When the switching network is in the second state, the buffer circuit is disconnected from the second capacitor and the first capacitor and the second capacitor are connected in parallel.

Variable controller and associated control methods

A circuit configured to receive a first and second voltages and generate an output voltage, the circuit comprising: a first capacitor configured to charge to a voltage equal a difference between the first voltage and the output voltage; a second capacitor configured to charge to a voltage equal to a difference between the first voltage and the second voltage; and a plurality of conductive paths coupled to the first and second capacitors. In a first state, the conductive paths are configured to cause the second capacitor to charge to the voltage equal to the difference between the first voltage and the second voltage. In a second state, the conductive paths are configured to cause the second capacitor to be connected in parallel with the first capacitor to cause the first capacitor to charge to the voltage equal to the difference between the first voltage and the output voltage.

Supply generator / supply modulator with switched-capacitor drive supply

A control circuit for a voltage regulator includes a divider coupled to the regulated output voltage to generate a divided voltage having a value that is a fraction of the regulated output voltage, an ADC responsive to the divided voltage to generate a feedback control signal, a digital compensator responsive to the feedback control signal and to a feedforward control signal scaled by a feedforward gain value to generate a compensator signal, and a pulse width modulator responsive to the compensator signal to generate a voltage control signal to control a switch of the voltage regulator. The digital compensator includes a register configured to store a value indicative of the input voltage and a feedforward gain unit configured to generate the feedforward gain value in response to the value indicative of the input voltage. In embodiments, the feedforward gain value is generated in response to the square of the value indicative of the input voltage. The feedforward gain value can be updated each time the value indicative of the input voltage is updated.

Converter digital control circuit with adaptive feedforward compensation

A control circuit for generating a feedforward control signal based on an input voltage includes a divider coupled to the input voltage to generate a divided voltage and a first buffer responsive to the divided voltage to generate a buffered voltage at an output of the first buffer. The control circuit also includes a first capacitor coupled to the first buffer output and configured to generate a feedforward current when there is a variation in the input voltage and a current mirror circuit including a current mirror output node at which a current mirror output voltage indicative of the input voltage variation is generated. A digitizing circuit is responsive to the current mirror output voltage to generate the feedforward control signal. A DC-DC converter and a method for generating a feedforward control signal based on an input voltage are also provided.

Control circuit

A tunable fractional phase locked loop (PLL) (hereinafter 'tunable PLL') is described herein and includes a controller configured to tune the tunable PLL to a range of frequencies corresponding to a frequency of the input clock signal. The tunable PLL includes a phase detector configured to receive an input clock signal and a feedback signal, a voltage controller oscillator (VCO) configured to receive the error signal from said phase detector and in response thereto to generate a VCO clock signal, a controller configured to generate a dithered division ratio having an average value corresponding to a ratio of a number of edges of the VCO clock signal generated in a cycle of the input clock signal, and a feedback module configured to generates a feedback signal to tune the PLL such that the PLL operates in the range of input frequencies of the input clock signal.

Tunable fractional phase locked loop

A control circuit for a voltage regulator includes a digital compensator having adaptive compensation to permit operation over different operating conditions. The digital compensator includes a gain parameter that is inversely proportional to the input voltage and is independent of the switching frequency. In embodiments, the voltage regulator has a crossover frequency established by at least one pole and at least one zero and the corner frequency of the converter output filter has a first fixed, predetermined relationship with respect to the switching frequency, a second fixed, predetermined relationship with respect to the crossover frequency, and a third fixed, predetermined relationship with respect to the at least one pole and at least one zero.

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Bedford, NH, United States of America

Kapil Kesarwani