Lsi Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Kapil Gaba

Shaohua Yang

Changyou Xu

Yuan Xing Lee

Wei Zhang

Richard Rauschmayer

Xuebin Wu

Qi Zuo

Yuqing Yang

Madhusudan Kalluri

Yoon Liong Liow

Harley Burger

Jonseung Park

Haitoa Xia

A power regulation system for a read channel of a data storage assembly includes a first voltage regulator for supplying power to the front-end decoder and a second voltage regulator for supplying power to the back-end codec. The second voltage regulator may conserve power reduce supply voltage to the back-end codec when the codec operates at a lower sampling frequency. The second voltage regulator may additionally increase supply voltage to the back-end codec in conjunction with an increase in sampling frequency. The system may additionally include a third voltage regulator for supplying a memory structure of the read channel with only the minimum required operating voltage to prevent leakage power.

Average power saving modes and power architecture for read channel product

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for calibration during data processing. As an example, a data processing system is discussed that includes a sample averaging circuit operable to average digital samples from an analog to digital converter circuit over multiple instances of an analog input to yield an X-average output, and a selector circuit operable to select one of the digital samples or the X-average output as a processing output.

Systems and methods for data retry using averaging process

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a pseudo-random sequence generator circuit, a decoder circuit, and a pseudo-random sequence reconstitution circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a detected output. The pseudo-random sequence generator circuit is operable to generate an interim data sequence and to generate a second data set based upon a combination of the detected output and the interim data sequence. The decoder circuit is operable to apply a data decode algorithm to a derivative of the second data set to yield a third data set.

Systems and methods for efficient data channel testing

Various embodiments of the present invention provide systems and methods for monitoring out of order data decoding. For example, a method for monitoring out of order data processing is provided that includes receiving a plurality of data sets that is associated with a plurality of identifiers with each of the plurality of identifiers indicates a respective one of the plurality of data sets; storing each of the plurality of identifiers in a FIFO memory in an order that the corresponding data sets of the plurality of data sets was received; processing the plurality of data sets such that at least one of the plurality of data sets is provided as an output data set; accessing the next available identifier from the FIFO memory; and asserting an out of order signal when the next available identifier is not the same as the identifier associated with the output data set.

Systems and methods for monitoring out of order data decoding

Various embodiments of the present invention provide systems and methods for updating detector parameters in a data processing circuit. For example, a data processing circuit is disclosed that includes a first detector circuit, a second detector circuit, and a calibration circuit. The first detector circuit is operable to receive a first data set and to apply a data detection algorithm to the first data set, and the second detector circuit is operable to receive a second data set and to apply the data detection algorithm to the second data set. The calibration circuit is operable to calculate a data detection parameter based upon a third data set. The data detection parameter is used by the first detector circuit in applying the data detection algorithm to the first data set during a period that the data detection parameter is used by the second detector circuit in applying the data detection algorithm to the second data set.

Systems and methods for updating detector parameters in a data processing circuit

Various embodiments of the present invention provide systems and methods for selecting between pre-coding and non-pre-coding. As an example, a data processing circuit is disclosed that includes: a first data detector circuit, a second data detector circuit, a first comparator circuit, a second comparator circuit, and a pre-code selection circuit. The first data detector circuit is selectably configurable to operate in a pre-coded state, and operable to apply a data detection algorithm on a data input to yield a first detected output. The second data detector circuit operable to apply the data detection algorithm to the data input to yield a second detected output without compensating for pre-coding. The first comparator circuit operable to compare the first detected output against a known input to yield a first comparison value, and the second comparator circuit operable to compare the second detected output against the known input to yield a second comparison value. The pre-code selection circuit is operable to determine a selectable configuration of the first data detector circuit based at least in part on the first comparison value and the second comparison value.

Systems and methods for data pre-coding calibration

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an increased iteration enable signal, a first detector circuit, a second detector circuit, and a data decoding circuit. The first detector circuit receives a data set and performs a data detection on the data set to provide a detected data set. The data decoding circuit receives a derivative of the detected data set and performs a decoding process to provide a decoded data set. The decoded data set is provided to the second detector circuit based at least in part on an assertion level of the increased iteration enable signal.

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Fremont, CA, United States of America

Kapil Gaba