Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Kaoru Tokushige

Haruki Toda

Hiroto Nakai

Shozo Saito

Hideo Kato

Masamichi Asano

Tomoharu Tanaka

Yoshiyuki Tanaka

Riichiro Shirota

Yoshihisa Iwata

Seiichi Aritome

Yasuo Itoh

Yutaka Okamoto

Masaki Momodomi

Hideko Odaira

Takashi Mori

Toshio Yamamura

Takehiko Hojo

Koji Sakui

Kenichi Imamiya

Hiroshi Nakamura

Kazuhisa Kanazawa

Masayoshi Nakane

Takanori Yoshimatsu

A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is configured to receive a clock signal and a first control signal, and output a plurality of data in response to the clock signal after the first control signal is asserted. After the first control signal is asserted, an internal signal which responds to the clock signal transits N times (N is a positive integer and greater than or equal to 2), then output of the data is started. At least one of the data is output at the transition after the output begins.

Semiconductor memory device

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Non-volatile semiconductor memory device and memory system using the same

A semiconductor memory device is disclosed, which includes a memory cell array including memory cells arranged in rows and columns, a word line, a bit line, a row decoder and a column decoder, a sense amplifier provided for each of the columns of the memory cell array, a write latch circuit configured to store externally input data and sets data of one row of the memory cell array in the sense amplifiers in test mode, a read latch circuit configured to store data of one row, which is read from the memory cell array and set in the sense amplifiers in test mode, a first comparison circuit configured to compare the data stored in the write latch circuit and the data stored in the read latch circuit, and a first comparison result register configured to store a comparison result of the first comparison circuit.

Semiconductor memory device and method of testing the device

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

A semiconductor device includes first to third functional areas parted each other by a boundary region on a semiconductor substrate. A memory block is formed in the first functional area and includes memory cells and a redundancy memory cell substituted for one memory cell. A functional circuit block is formed in the second functional area and connected with the memory block via an interconnection line. A program interconnection block is formed in the third functional area so that it does not overlap with the interconnection line and includes a program interconnection section which forms a program forming a signal path so that a defective memory cell is substituted by the redundancy memory cell. A data transfer section extends over from the program interconnection block to the memory block and transfers program information relevant to the program of the program interconnection section to the memory block.

Semiconductor device having a redundancy function

A method of accessing a semiconductor device that operates in synchronism with a clock signal, including fetching information indicating a memory cell location in a memory cell array in synchronism with the clock signal, determining first data of a plurality of data to be transferred sequentially, decoding the information indicating the memory cell location in the memory cell array and designating the memory cell, receiving data stored in the memory cell designated by the information indicating the memory cell location in the memory cell array in synchronism with the clock signal after a predetermined number of cycles of the clock signal, and outputting a plurality of data stored in the memory cells in synchronism with the clock signal and storing a plurality of input data in the memory cells in synchronism with the clock signal.

A semiconductor device includes a memory cell array, a counting section, a control section, a specification section and a data input/output section. The counting section configured to count transition of the clock signal and determine first data of a plurality of data to be transferred sequentially. The control section configured to fetch information indicating a memory cell location in the memory cell array in response to a counting result of the counting section and control consecutive input and output of a plurality of data stored in the memory cell array every cycle of the clock signal. The specification section configured to decode the information fetched by the control section and designate a memory cell in the memory cell array. The data input/output section configured to input data to or output data from the memory cell designated by the specification section, wherein input and output of the data are time-shared.

A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for entering them in an active state; a data input/output (I/O) circuit .for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal, provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.

A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit under a control based on a read-out/write-in signal provided from an external section; a counter circuit for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit and the data I/O operation of the data I/O circuit, so that the memory access operations for the memory cell group are controlled.

Non-volatile semiconductor memory device with an improved verify voltage generator

A block size buffer and block address pre-decoder are provided for a flash memory. At the time of data erase, the size of a block to be erased is input to the block size buffer and a set of block addresses is input to the block address pre-decoder. An output signal of the block size buffer is supplied to and decoded by the block address pre-decoder, a row decoder is controlled based on the result of pre-decoding, and a plurality of addressing including the above block address as a top address are selected in a multiple manner. Then, a plurality of successive blocks are simultaneously selected to simultaneously erase data in the memory cells in the plurality of blocks.

Nonvolatile semiconductor memory device whose addresses are selected in

A nonvolatile semiconductor memory device comprises a plurality of nonvolatile memory cells, which can be electrically programmed and erased, the plurality of nonvolatile memory cells divided into a plurality of blocks, a block erase circuit for erasing the plurality of nonvolatile memory cells contained in the plurality of blocks at the same time per block, erase operation times storage section for storing the number of erase operations of the nonvolatile memory cells to be erased at the same time by the block erase circuit per block in a number of erase operation storage region, and read time setting section for setting the read time based on the number of the erase operations stored in the number of erase operation storage region at the time of reading the storage data in the nonvolatile memory cells.

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Yokohama, Japan

Kaoru Tokushige