Sony Corporation

Kaoru Sekigawa

Yoshiyuki Yahagi

Masami Sato

Masami Tsubaki

Takeshi Ishihara

Toshiyuki Yamazaki

Yukihiro Maruyama

Koji Kosaka

Shuhei Kanaoka

Yukihira Maruyama

Hiromi Inoue

A matrix switcher includes a switcher unit having connection switches provided at intersections of input signal lines and output signal lines and a control unit having a main controller and a backup controller. The backup controller operates a Web server program to transfer a setup command to the main controller upon receiving the setup command. The main controller executes: processing of switching a connection relation between the input signal lines and output signal lines in the switcher unit; processing of transferring a switching command to another matrix switcher upon receiving the switching command for another switcher; processing of setting up the matrix switcher upon receiving the setup command for the switcher; and processing of transferring the setup command to another matrix switcher upon receiving the setup command for another switcher.

Matrix switcher and method of controlling matrix switcher

A signal processing system manages terminal numbers as a whole system without being affected by exchange of substrates and performs signal processing of intended object. A control unit sequentially assigns terminal numbers to substrates in numerical order of slots of each kind and validates only terminal numbers regarding the slot where the relevant kind of substrate is inserted. Information indicating regions of different terminal numbers in a space where the number of input/output terminals are more than those of the whole system is retained corresponding to the substrate of each kind. Based on a command specifying input/output signals by the terminal numbers in the space, terminal numbers of a substrate of the kind corresponding to the region including the specified terminal numbers are obtained, and processing corresponding to the command is executed only when those terminal numbers are valid in the substrate of the kind.

Signal processing system and routing switcher method for managing the validity of computer terminal numbers

An apparatus for editing an input information signal is capable of preventing breaks in sound even if the length of a cut is edited as extremely short. In the editing apparatus, the input digital information signal is temporarily stored in a recording buffer means. Further, the digital information signal is read at a speed faster than its write speed and recorded on a recording medium. The digital information signal read from the recording medium is written into a reproducing buffer means. Thereafter, the digital information signal is read from the reproducing buffer means at a speed slower than its write speed, after which it is restored to an analog information signal. A control means for controlling recording and reproduction controls whether an information signal should be recorded in an auxiliary area according to the presence or absence of a splice recording, and monitors whether a point to be edited has been changed to a length causing a break in sound due to editing. Thus, even if the length of a redefined cut is less than or equal to a limit length, edit working allows the prevention of the length of the cut being less than or equal to the limit length. It is thus possible to reliably prevent the occurrence of breaks in reproduced sound.

Method of recording and reproducing information signals and apparatus

A variable speed reproduction of speech from memory depending on the indication of a jog dial, is accomplished by buffer memory (23) for speech sound and a jog dial (17) for controlling a read speed from this memory. Speech sound data is read out from the buffer memory (23) at a speed corresponding to the indication of the jog dial (17). The speech sound data is reproduced, independent of the jog dial (17), from a tape (13) and is written into the memory (23). A capstan motor drive circuit (18) detects the difference between the read address and the write address of the memory (23) and controls the reproduction speed of the sound speech data from the tape (13) in accordance with this difference. Since the read speed is directly controlled for the memory (23), no time delay exists between the speed command and the actual variable-speed reproduction. The address difference between write and read of the memory (23) is always monitored to keep the buffer from becoming empty so that continuous reproduction can be made, and so that, when the speech sound is edited, variable-speed continuous reproduction can be made for speech editing by the buffer memory (23) alone.

Digital sound reproducing and editing device for recording sound with

Digital sound reproducing and editing device with variable-speed

A method and an apparatus for automatically editing audio signals by determining an editing section on a recording medium having the signals recorded thereon. A first editing point is searched for on the recording medium, and the location of that point is stored in a memory. A second editing point is searched for on the recording medium. The location of the first editing point is compared with that of the second editing point. One of the two locations is set as an in-point and the other location as an out-point in accordance with the result of the comparison. The editing section determined by the in- and out-points is displayed on a screen.

Method and apparatus for automatically editing audio signals

A digital tape recorder is provided in which main digital signals and time code signals are recorded on a magnetic tape after realization of the timing concurrence between these signals. To this end, a delay correction circuit 23 for delaying the input time code signals by a delay time at an A/D converter 13 or a delay time at a digital input interfacing circuit 16 are provided. The input time code signals delayed by the delay correction circuit 23 and main digital signals from the A/D converter 13 or the digital input interfacing circuit 16 are transmitted to an encoder 17 and recorded on the tape 30 in such a state in which the in-line relationship or timing concurrence is maintained between these main digital signals and the time code signals.

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Kanagawa, Japan

Kaoru Sekigawa