Kabushiki Kaisha Toshiba

Kaoru Nakagawa

Masaru Koyanagi

Takahiko Hara

Satoru Takase

Toshiki Hisada

Hideo Mukai

Natsuki Kushiyama

Katsuki Matsudera

Kazuhide Yoneya

Sadayuki Yokoyama

Fujio Masuoka

Hiroshi Iwahashi

Masamichi Asano

Katsuyuki Fujita

Mitsugi Ogura

Teruyuki Hiyoshi

Yoshiaki Takeuchi

Katsumi Abe

Hiroyuki Koinuma

Kenji Natori

Katsushi Nagaba

Seiro Imai

Yoshio Yamamoto

Kenji Komatsu

Nobutaka Matsuoka

Tohru Yoshikawa

In a DRAM semiconductor memory device, a DRAM semiconductor memory device disclosed herein comprises a first spare element SWL provided for each of a plurality of normal banks BANK -BANK formed by dividing a memory cell array into a plurality of sections, a second spare element SWL provided for a spare bank BANKSP different from the normal banks, a plurality of first spare decoders SRD -SRD for selectively operating the first spare element, a plurality of second spare decoders SRD -SRD for selectivedly operating the second spare element, and a substitution-control circuits FS -FS , RWLON -RWLON , SRDact -SRDact for selectively assigning the second spare elements to arbitrary banks of the plurality of normal banks. With the above structure, the total number of the spare elements of the defective memory cells of the DRAM can be reduced while the relieving ratio is being maintained. As a result, the area efficiency of the redundant circuit on the chip can be improved.

Semiconductor memory device

In a DRAM semiconductor memory device, a DRAM semiconductor memory device disclosed herein comprises a first spare element SWL provided for each of a plurality of normal banks BANK0-BANK15 formed by dividing a memory cell array into a plurality of sections, a second spare element SWL provided for a spare bank BANKSP different from the normal banks, a plurality of first spare decoders SRD0-SRD3 for selectively operating the first spare element, a plurality of second spare decoders SRD0-SRD3 for selectively operating the second spare element, and a substitution-control circuits FS0a-FS27a, RWLON1-RWLON2, SRDact0-SRDact3 for selectively assigning the second spare elements to arbitrary banks of the plurality of normal banks. With the above structure, the total number of the spare elements of the defective memory cells of the DRAM can be reduced while the relieving ratio is being maintained. As a result, the area efficiency of the redundant circuit on the chip can be improved.

A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

Dynamic random access memory device and semiconductor integrated circuit device

The semiconductor memory includes a memory cell which handles a clock signal, an address fetch and a command circuit. The memory cell is designated by an address signal and stores data. The clock signal is supplied thereto so as to provide timing for an access to the memory cell, and the clock signal has a leading edge and a trailing edge. The address fetch circuit fetches the address signal for designating the memory cell in synchronism with both of the leading edge and trailing edge of the clock signal. The command circuit fetches a command signal for instructing the access to the memory cell in synchronism with both of the leading edge and the trailing edge of the clock signal.

Semiconductor memory having double data rate transfer technique

A semiconductor integrated circuit is provided with a plurality of selectors, each of which is connected to a corresponding one of a plurality of data lines through which bit data read out from a corresponding one of a plurality of cell array blocks is transmitted, wherein a selector control circuit controls selection operations of the selectors based on a control clock so that the selectors select and output readout data in the order in which the bit data are read out from the corresponding cell array blocks.

Clock synchronization semiconductor memory device sequentially outputting data bit by bit

A semiconductor memory has an output data latch circuit controlled in response to a clock signal shifted by a half period from a control clock input to n one-bit shift register stages. The memory device includes a plurality of read data latch circuits, as well as a plurality of write or address data latch circuits, coupled to the n one-bit shift register stages and to a plurality of selector or multiplexor circuits. A noise filter is inserted in a clock input supply path to the n one-bit shift register stages but is not inserted in a clock input supply path to the output data latch circuit.

Serial input/output semiconductor memory including an output data latch

There is enclosed a semiconductor memory device having an internal circuit including a plurality of memory cells which can store data thereinto, respectively, to output, as a first output signal, data in a memory cell selected by an address signal, and an output circuit adapted to receive the first output signal to output a second output signal. Power from the same external power supply is delivered to the internal circuit and the output circuit through power supply terminals, and power supply wirings. The power is delivered to the internal circuit through a resistor formed in the middle of the power supply wirings.

In an electrically erasable non-volatile semiconductor memory device, a plurality of non-volatile semiconductor memory cells are arranged in a matrix form and are connected to corresponding ones of row and column lines. In a data writing mode, a first voltage Vp at is applied to the column lines so that the drains of the memory cells are maintained at a drain potential, and a second voltage is applied to the row lines so that a sum level of the drain potential and the threshold voltage of the memory cell is not smaller than the floating gate potential of the memory cell.

Electrically erasable non-volatile semiconductor device

In a nonvolatile semiconductor memory, each of a plurality of memory cells arranged in the form of a matrix includes a p-type semiconductor region, an n-type source connected to the ground potential, an n-type drain formed in a longitudinal direction with respect to the source, a channel region located between the source and the drain, a control gate transversely extending and formed above the channel region, intervening a first insulating film, a floating gate formed in the first insulating film above the channel region, and an erase gate formed in the first insulating film so as to spatially overlap one end of the floating gate. The memory further includes an erase line extending in the longitudinal direction, formed in the first insulating film and connected to the erase gate, and a data line, connected to the drain. First and second memory cells of the plurality of memory cells are arranged to be adjacent to one another in the transverse direction to constitute a first memory cell pair. The sources of the first and second memory cells are exclusively connected to one another. The sources of the adjacent memory cell series in the transverse direction are independently formed. The erase gate line connected to the erase gate and the source do not cross over each other.

Flash erasable and programmable nonvolatile semiconductor memory

The present semiconductor device comprises a first semiconductor substrate, an oxide film formed on the substrate and a second semiconductor substrate bonded to the oxide film. In particular, the semiconductor substrate further has a monocrystalline silicon layer which is formed by an epitaxial growth method on the second semiconductor substrate. Circuit elements are formed within the monocrystalline silicon layer.

Method of manufacturing an soi-type semiconductor device

A first circuit is made up of a first clocked inverter and a first modified clocked inverter. A second circuit is made up of a second clocked inverter and a second modified clocked inverter. The first circuit has substantially the same circuit arrangement as that of the second circuit. The first circuit operates in response of the output signal from the second circuit, and vice versa.

Latch circuit constructed with MOS transistors and shift register using

A semiconductor integrated circuit comprises a three-valued logic circuit connected to receive an output signal of a logic circuit to receive at one input a control clock signal and at the other input an input signal, and a flip-flop circuit composed of a clocked inverter to receive the output signal of the three-valued logic circuit, and another inverter.

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Kawasaki, Japan

Kaoru Nakagawa