Other

Research Development Corporation

Zaidan Hojin Handotai Kenkyu Shinkokai

Junichi Nishizawa

Kaoru Motoya

Jun-ichi Nishizawa

Takashige Tamamushi

Akira Ito

A recess-gate type static induction transistor having a high breakdown voltage is provided, which includes an n-type channel region provided over an n.sup.+ -type drain region, p.sup.+ -type elongated gate regions provided in grooves of the channel region, n.sup.+ -type elongated regions formed on the channel region so as to be arranged in parallel with the gate regions, each of which is disposed between the gate regions, and a p.sup.+ -type guard ring region provided in the channel region and arranged to surround the gate regions. The elongated gate regions are coupled to the guard ring region at both edges. In addition, the outer-most elongated gate regions are coupled to the guard ring region along the longitudinal direction, respectively, thereby increasing the breakdown voltage of the device. Further, gate and source contact pads are provided only on the guard ring region so as to be opposed, thereby reducing unwanted parasitic capacitances between gate and drain regions and between gate and source regions.

High frequency static induction transistor having high output

In a static induction transistor of thermionic emission type, its gate region is formed of a semiconductor having a forbidden band gap larger than that of a semiconductor forming its channel region, and the distance between a source region and the intrinsic gate region is selected to be smaller than the mean free path of carriers so as to permit the thermionic emission. Such a vertical structure transistor is also applied to an integrated circuit.

Thermionic emission type static induction transistor and its integrated

In a static induction transistor of tunnel injection type, a tunnel injection region is formed between its source region and channel region, and its gate region is formed of a semiconductor having a forbidden band larger than that of said channel region and contacting partially or wholly with the surface of said channel region. Such a transistor is also applied to an integrated circuit.

Tunnel injection type static transistor and its integrated circuit

An extremely-high frequency semiconductor oscillator which produces a large but substantially noise-free output power with minimized fluctuation of output power for changes in device temperature is realized by using, as its power producing component, a semiconductor transit time diode having a frequency-dependent negative resistance mounted in a cavity resonator of a wave guide means provided with a tuning short at one side of the waveguide means and being designed to perform carrier injection by a combination of tunnel and avalanche phenomena.

Extremely-high frequency semiconductor oscillator using transit time

A junction field effect transistor has a wide bandgap heterojunction gate. The source to gate spacing is less than the carrier mean free path for ballistic transport. The channel thickness is less than twice the Debye length.

Heterojunction gate ballistic JFET with channel thinner than Debye length

The present invention relates to a semiconductor FET or SIT type photoelectric transducer comprising a source and a drain which are main electrode regions of high impurity density; a high resistivity or intrinsic semiconductor region of the same conductivity type as the main electrode regions and formed therebetween as a current path; and a plurality of gate regions formed by high impurity density regions reverse in conductivity from the main electrode regions and formed in the current path, for controlling a main current; wherein the distance W.sub.1 between a first one of the gate regions on both sides of the source and the source or the drain is greater than the distance W.sub.2 between the other gate region and the source or drain (W.sub.1 &gt;W.sub.2), and wherein the size of the first gate region is smaller than the diffusion length of carriers to be stored in the first gate region. Briefly stated, the present invention is intended to enhance the function of the first gate by selecting the size of the first gate region for storing optical information within the diffusion length of the carriers stored therein, in addition to the selection of the aforementioned distances W.sub.1 and W.sub.2.

Growing community of inventors

Sendai, Japan

Kaoru Motoya