Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Mitsubishi Electric System Lsi Design Corporation

Kaoru Motonami

Tomonori Okudaira

Natsuo Ajika

Hideaki Arima

Yoshinori Okumura

Atsushi Hachisuka

Atsushi Narazaki

Yasuyoshi Itoh

Yasushi Matsui

Shigeto Honda

Shigeru Shiratake

Satoshi Hamamoto

Masatoshi Kimura

Takaaki Murakami

Yuichi Yokoyama

Masao Nagatomo

Kazunari Nakata

Makoto Ohi

Hiroaki Sekikawa

Hiroshi Matsuo

Kenji Yasumura

Ryoichi Fujii

Ritsuko Gotoda

Kenji Morisawa

Hisaaki Yoshida

Kazumasa Mitsunaga

Tomohiro Ikeda

Hidetada Tokioka

Makoto Hatakenaka

Takeshi Iwamoto

Atsushi Amo

Kazushi Yamayoshi

Nobuo Fujiwara

Toru Takeguchi

Kakutaro Suda

Michio Nakajima

Takuji Imamura

Mutsumi Tsuda

Yasuhiro Ido

Akira Kitaguchi

Hideki Doi

Takekazu Yamashita

Akira Yamashita

Tomoyuki Irizumi

Kiyoyuki Shiroshima

Atsunori Nishiura

Rui Toyota

Yasutoshi Yashiki

Tomoya Hirata

Kazuhide Kawabe

Katumi Suizu

Ayumu Onoyama

A thermoelectric converter includes a substrate and two thermoelectric elements that may include a flat portion and a concave portion. The thermoelectric elements each include one end that contacts with the thermoelectric element and an other end that contacts with thermoelectric element at a bottom surface of the concave portion. The thermoelectric elements are each positioned to be suspended across a space defined by the concave portion. The thermoelectric converter can be manufactured through photolithographic process, and can be incorporated into an exhaust gas recirculation device.

Thermoelectric converter and manufacturing method for manufacturing thermoelectric converter

A method for diagnosing a solar cell module includes an analysis of measuring frequency characteristics including a resonance point of impedance between two poles of a solar cell module, and frequency characteristics including a resonance point of impedance between an output cable and a frame, and determining equivalent circuit constants of the solar cell module, and a determination of comparing the equivalent circuit constants determined in the analysis with equivalent circuit constants obtained previously to determine change in condition of the solar cell module.

Method for diagnosing solar cell module, and diagnostic circuit and diagnostic system for solar cell module

In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.

High breakdown voltage semiconductor device having a resurf layer

A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.

Power semiconductor device and method of manufacturing the same

A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed.

Method of manufacturing semiconductor device

A semiconductor device includes a base layer that has a first conductivity type, a source layer that is formed on the base layer and has a second conductivity type, and an insulating film that is formed on the source layer. The semiconductor device further includes a plurality of gate structures that penetrate the base layer, and a plurality of conductive parts that penetrate the insulating film and the source layer and electrically connect the source layer and the base layer to each other. The gate structures are formed in a stripe shape in plan view. Parts in which the conductive portion is connected to the base layer are formed in a stripe shape in plan view, and are formed between the gate structures. Further, a dimension of the part in which the source layer and the base layer are in contact with each other between the gate structure and the conductive portion is 0.36 &#x3bc;m or more.

Semiconductor device

In a thin film transistor using a polycrystalline semiconductor film, when a storage capacitor is formed, it is often that a polycrystalline semiconductor film is used also in one electrode of the capacity. In a display device having a storage capacitor and thin film transistor which have a polycrystalline semiconductor film, the storage capacitor exhibits a voltage dependency due to the semiconductor film, and hence a display failure is caused. In the display device of the invention, a metal conductive filmis stacked above a semiconductor layermade of a polycrystalline semiconductor film which is used as a lower electrode of a storage capacitor

Display device and method of producing the same

An additional circuit is formed on a glass substrate, and a passivation film is deposited thereon. After an insulation film is deposited on the passivation film, a contact hole is formed, and a signal line is deposited and connected to the additional circuit. After the signal line and the insulation film are patterned, an organic insulation film is formed, to thereby have a surface of an uneven configuration depending on a step formed by the signal line and the insulation film. A reflective electrode is formed on the organic insulation film, to thereby have a surface of an uneven configuration. This eliminates the need to perform a photolithography process step for the formation of the surface of the organic insulation film in the uneven configuration, thereby reducing manufacturing costs.

Array substrate for an image display device

A semiconductor device comprises a glass substrate serving as a substrate having an insulated surface and a silicon layer located on a position overlapping with this glass substrate. The silicon layer includes an amorphous gettering region. Preferably, the silicon layer includes a main region serving as an active element region, and the gettering region is preferably included in the remaining portion of the silicon layer excluding the main region. Preferably, the silicon layer may include a portion serving as an active region of a thin-film transistor.

A semiconductor device includes: an insulation layer; a fuse layer extending on the insulation layer in one direction and disconnected through light radiation to control a redundant circuit; a pseudo fuse layer on the insulation layer along at least one side of the fuse layer; another insulation layer covering the fuse layer and the pseudo fuse layer; and a protection film formed on another insulation layer and having an opening in a region opposite to the fuse layer. Fuse layers having a spacing of less than 4 &mgr;m or 4.5 to 5.5 &mgr;m. Such a structure allows a semiconductor device with a fuse layer capable of being disconnected reliably and providing a smaller blow trace.

Semiconductor device having a fuse layer

A semiconductor device having a memory device and a logic device formed together on a single chip is provided. A first element region and a second element region of a semiconductor substrate are formed spaced apart from each other with an isolation region therebetween. A floating conductive film is provided on the isolation region.

A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.

Semiconductor integrated circuit including a capacitor and a fuse element

There are provided a semiconductor device, which includes an element isolating oxide film having a good upper flatness, and a method of manufacturing the same. Assuming that t.sub.G represents a thickness of a gate electrode layer 6, a height t.sub.U to an upper surface of a thickest portion of element isolating oxide film 4 from an upper surface of a gate insulating film 5 and an acute angle .theta.i defined between the upper surfaces of element isolating oxide film 4 and gate insulating film are set within ranges expressed by the formula of {.theta.i, t.sub.U .linevert split.0.ltoreq..theta.i.ltoreq.56.6.degree., 0.ltoreq.t.sub.U .ltoreq.0.82t.sub.G }. Thereby, an unetched portion does not remain at an etching step for patterning the gate electrode layer to be formed later. This prevents short-circuit of the gate electrode. Since the element isolating oxide film has the improved flatness, a quantity of overetching in an active region can be reduced at a step of patterning the gate electrode. This prevents shaving of the gate insulating film and the underlying substrate surface.

Semiconductor device having an element isolating oxide film and method

In a semiconductor device having a DRAM memo cell and a peripheral circuit, source/drain regions of transistors composing the memory cell are not silicided to restrict a junction leak and to improve a refresh characteristic; surfaces of source/drain regions and gate electrodes of transistors composing the peripheral circuit are silicided to reduce resistance of contacts and resistance of wirings for enabling a high-speed operation; side walls made of insulating material are formed on sides of the gate electrodes of the transistor composing the peripheral circuit to serve as a mask when impurities are injected for forming the source/drain regions; and insulating material laminated in the memory cell serves as a mask against siliciding.

Semiconductor device and method of producing the same

Semiconductor device and method of manufacturing the same

Growing community of inventors

Hyogo, Japan

Kaoru Motonami