Nec Corporation

Nec Electronics Corporation

Kaoru Mikagi

Ken Inoue

Tomohiro Nishiyama

Masamoto Tago

Tetuya Tao

Kuniko Miyakawa

Kunihiro Fujii

Akira Furuya

Hidemitsu Aoki

Hiroaki Tomimori

Nobuaki Hamanaka

Tetsuya Tao

Koji Arita

Ryohei Kitao

A highly reliable semiconductor chip electrode structure allowing control of interface reaction of bonding sections even in the case of using two- or three-element solder used conventionally is disclosed. A solder alloy making layer for preventing dissolving and diffusion of tin into tin-based lead free solder is thinly formed on a UBM layer. The tin-based solder is supplied in solder paste or solder ball form. A combined solder alloy layer composed of a combination of intermetallic compounds, one of tin and the solder alloy making layer, and one of tin and the UBM layer, is formed by heating and melting.

Semiconductor device, manufacturing method and apparatus for the same

An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.

Process for making a semiconductor device having a roughened surface

Semiconductor device having a roughened surface

In copper plating using a damascene method, in order to prevent cost rise, dishing, erosion and the like due to the protrusion of plating on the dense wiring area to increase the time for CMP polishing, the copper plating is performed so that the current step of the copper plating has only one step for flowing current in the direction opposite to the direction of growing the plating as shown in FIG.. In this time, this opposite direction current step is performed under the condition of a current-time product within a range between 1.0 and 120 mA&#xd7;sec/cm.

Method of manufacturing semiconductor device having damascene interconnection

A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of forming the metal-silicide layer on the surface of the impurity-diffused region between the steps of implanting impurities to form an impurity-implanted region and annealing for reactions of cobalt and silicon of the diffused layer. The above-mentioned method of forming the metal-silicide layer on the surface of the impurity-diffused region proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Method for forming a silicide of metal with a high melting point in a semiconductor device

A silicide film is selectively formed at least on diffusion layers of a MOS transistor. In the method for forming the silicide film includes, a first metal film is selectively formed at least on diffusion layers. A first annealing is applied to allow at least the diffusion layers to react with the first metal film. A part of the sidewalls is removed to form a gap with reacted film of the first metal film. A second annealing is performed at a temperature higher than that of the first annealing to form a reacted film. This makes it possible to form a silicide film having preferable electric characteristics on a gate and diffusion layers being fine in dimension and high in impurity concentration, in a self-aligning fashion without producing &ldquo;bite of silicide.&rdquo;

Method for forming a silicide film on gate electrodes and diffusion layers of MOS transistors

A method for forming a silicide of a metal with high-melting-point in a semiconductor device includes the step of removing a higher-density impurity area which acts for prevention of refractory-metal-silicification of diffused regions between the steps of implanting impurities to form an impurity-implanted region and annealing for refractory-metal-silicification of the diffused layer. The refractory-metal-silicification of the diffused regions proceeds smoothly to thereby prevent degradation of the initial gate withstand voltage and a higher sheet resistance.

Method for forming a refractory-metal-silicide layer in a semiconductor device

Silicide films having a high heat-resistance are formed on a gate electrode, simultaneously with silicide films having good junction leakage characteristics on diffusion layers. A transistor includes a polycrystalline silicon gate electrode, a gate insulating film, a diffusion layer, and sidewalls on a silicon substrate isolated by an element isolation oxide film. A first silicide film and a second silicide film are formed on the gate electrode and on the diffusion layer, respectively. The first silicide film is thicker than the second silicide film.

Semiconductor device having silicide films on a gate electrode and a diffusion layer and manufacturing method thereof

A semiconductor device having: a first interconnect or electrode formed on a substrate; an organic insulation film which is formed covering the first interconnect or electrode and in which an interconnect trench and an interlayer connection hole reaching from the interconnect trench to the first interconnect or electrode are formed; an inorganic insulation film which is formed covering the side of the interconnect trench and the interlayer connection hole, and into at least surface part of which nitrogen is introduced; a second interconnect or electrode buried into the interconnect trench through the inorganic insulation film; and a buried conductive layer which is formed in the interlayer connection hole and connects between the between the first interconnect or electrode and the second interconnect or electrode.

Semiconductor device and method for making the same

A method of forming a cobalt silicide layer on a silicon region comprises the steps of: forming a TEOS oxide film on a surface of the silicon region; carrying out an ion-implantation process for implanting ions through the TEOS oxide film into the silicon region; carrying out a heat treatment to activate the ions implanted in the silicon region, whereby a silicidation reaction inhibitor layer concurrently formed on an interface between the TEOS oxide film and the surface of the silicon region; carrying out a dry etching to remove laminations of the TEOS oxide film and the silicidation reaction inhibitor layer from the surface of the silicon region; carrying out a cleaning process for cleaning the surface of the silicon region by subjecting the surface of the silicon region to an acidic solution and subsequently to a diluted hydrofluoric acid solution; and forming a cobalt silicide layer on the surface of the silicon region.

Method of forming a cobalt silicide layer by use of a TEOS through oxide film for ion-implantation process

A semiconductor device having a metal interconnection includes an insulating film provided on a semiconductor substrate via a diffusion layer. An interlayer contact hole is formed in the insulating film. A metal silicide layer is provided at the bottom of the interlayer contact hole. A first conductive film comprises a single or a plurality of metal films provided on the insulating film and the interlayer contact hole. A second conductive film is provided in the interlayer contact hole. A third conductive film is provided on the first conductive film and the second conductive film. A fourth conductive film is provided on the third conductive film. This semiconductor device has improved durability with respect to electromigration or stress migration. Even when the interconnection has a multilevel structure, the contact resistance can be reduced by causing the interlayer contact hole portions to contact one another by the same kind of metal.

Growing community of inventors

Tokyo, Japan

Kaoru Mikagi