Hitachi, Ltd.

Kaoru Koyu

Mitsuo Usami

Noboru Shiozawa

Atsushi Shimizu

Toshio Yamada

Tatsuya Kimura

Tohru Kobayashi

Masato Hamamoto

Hiromasa Katoh

Kazuyoshi Satoh

In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

Semiconductor integrated circuit device with a plurality of logic

A unitary semiconductor integrated circuit is constructed using a non-threshold logic NTL circuit for a circuit which has a light load or a light load driving capability, using an NTL circuit additionally provided with an emitter-follower output circuit for effecting a circuit having a comparatively heavy load, and using a super pull-down logic (SPL) circuit for effecting a circuit having a heavy load. The NTL circuit thereof which receives an output signal generated by the emitter-follower output circuit or from the SPL circuit associated with a preceding logic gate circuit stage uses, as its operating voltage, the operating voltage of the emitter-follower output circuit or that of the SPL circuit.

High speed IC device empolying non-threshold logic circuits to provide

A semiconductor integrated circuit wherein an input circuit is formed by a phase split circuit consisting of a bipolar transistor which outputs an inverted output from the collector and non-inverted output from the emitter, the emitter follower output circuit is driven by an inverted output of the phase split circuit, meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit.

High speed TTL buffer circuit which is resistive to the influence of

Growing community of inventors

Ohme, Japan

Kaoru Koyu