Olympus Corporation

Kaoru Kotoda

Satoshi Tanaka

Takayuki Sato

Kazuhiro Takizawa

Motoo Azuma

Hisashi Nishimura

Naruyasu Kobayashi

A phase control unit compares a phase of a display synchronization signal with a phase of a clock signal generated from a clock signal generated by an imaging clock generating unit, and controls oscillation of the imaging clock generating unit based on a result of the comparison. A drive signal generating unit generates a drive signal that drives a CMOS sensor based on a multiplication clock signal synchronized to the clock signal.

Electronic endoscopic apparatus

A CMOS sensor converts optical information into an electric signal, and outputs the converted electric signal as an image signal. An imaging clock generating unit generates an imaging clock acting as a source of a drive signal that drives the CMOS sensor. A drive signal generating unit generates an imaging synchronization signal and a drive signal based on the imaging clock. A display clock generating unit generates a display clock. A display synchronization signal generating unit generates a display synchronization signal based on the display clock. A phase comparing unit compares a phase of the imaging synchronization signal with a phase of the display clock, and controls oscillation of the display clock generating unit based on a result of the comparison.

A phase comparing unit compares a phase of an imaging-side synchronization signal with a phase of a display-side clock, and controls oscillation of a display-side clock generating unit based on a result of the comparison. A display timing adjusting unit receives a video signal output from an endoscope at a timing based on the imaging-side synchronization signal and adjusts a synchronization timing of the received video signal to a synchronization timing based on a display-side synchronization signal.

Electronic endoscope apparatus

An electronic endoscopic apparatus includes an endoscopic scope and an image processing processor. The endoscopic scope includes a solid-state imaging device, an imaging-side multiplying unit, and an imaging synchronization signal generating unit. The image processing processor includes a display clock generating unit, a monitor synchronization signal generating unit, a master imaging clock generating unit, a processor-side multiplying/dividing unit, a phase-comparison oscillation control unit, and a display timing adjustment unit.

Image-pickup sections and an image-communicating/processing sectionare connected by a single bus. Following the output of the image data, an output-controlling section in one of the image-pickup sections outputs an image-data-ending pattern, which indicates the end of outputting the image data, to a bus. An ending-pattern-detecting section in another image-pickup section detects the image-data-ending pattern, and outputs an image-pickup-operation-starting signal. The another image-pickup section starts an image-pickup operation and output of the image data based on the image-pickup-operation-starting signal.

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Tokyo, Japan

Kaoru Kotoda