Ohkuchi Materials Co., Ltd.

Sh Materials Co., Ltd.

Kaoru Hishiki

Keiichi Otaki

Hidehiko Sasaki

Kotaro Tomeoka

Ichinori Iidani

Hiroki Nakayama

Shunichi Kidoguchi

Yasuo Toyoshi

Ryouichi Yoshimoto

Kazunori Iitani

A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering only top faces on the upper surface side of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction &#x3c;101&#x3e; occupies a largest proportion among the crystal directions &#x3c;001&#x3e;, &#x3c;111&#x3e;, and &#x3c;101&#x3e;. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

Lead frame

A substrate for mounting a semiconductor element thereon has columnar terminal portions formed by concavities provided on an upper surface of a metal plate made of a copper-based material, and is provided with a roughened silver plating layer having acicular projections, applied, as the outermost plating layer, to top faces of the columnar terminal portions. The roughened silver plating layer has a crystal structure in which the crystal direction &#x3c;101&#x3e; occupies a largest proportion among the crystal directions &#x3c;001&#x3e;, &#x3c;111&#x3e; and &#x3c;101&#x3e;. The substrate for mounting a semiconductor element thereon facilitates thin design of semiconductor packages produced by flip-chip mounting, can be manufactured with improved productivity owing to reduction in cost and operation time, achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

Substrate for mounting semiconductor element

A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering top faces and faces that form concavities or a through hole between the top faces and bottom faces of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction &#x3c;101&#x3e; occupies a largest proportion among the crystal directions &#x3c;001&#x3e;, &#x3c;111&#x3e;, and &#x3c;101&#x3e;. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

A device for mounting a semiconductor element includes a metal plate serving as a base, a roughened silver plating layer with acicular projections, formed on at least either of: (a) top faces; and (b) faces that form concavities or through holes between the top faces and bottom faces; of the metal plate, and a reinforcing plating layer covering, as an outermost plating layer, an outer surface of the acicular projections in the roughened silver plating layer. The roughened silver plating layer has a crystal structure in which the crystal direction &#x3c;101&#x3e; occupies a largest proportion among the crystal directions &#x3c;001&#x3e;, &#x3c;111&#x3e;, and &#x3c;101&#x3e;. An outer surface of the reinforcing plating layer is shaped to have acicular projections with a surface area ratio of 1.30 or more and 6.00 or less to the corresponding smooth surface, as inheriting the shape of the acicular projections in the roughened silver plating layer.

Device for mounting semiconductor element, lead frame, and substrate for mounting semiconductor element

A lead frame includes a lead frame substrate made of a copper-based material, plating layers composed of nickel, palladium and gold layers laminated in this order on top faces and bottom faces of the lead frame substrate, and a roughened silver plating layer having acicular projections, provided as an outermost plating layer and covering faces of the lead frame substrate that form concavities or a through hole between the top faces and the bottom faces of the lead frame substrate. The roughened silver plating layer has a crystal structure in which the crystal direction &#x3c;101&#x3e; occupies a largest proportion among the crystal directions &#x3c;001&#x3e;, &#x3c;111&#x3e; and &#x3c;101&#x3e;. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

A substrate for mounting a semiconductor element thereon includes a metal plate and columnar terminal portions composed only of plating layers and formed on one-side surface of the metal plate. The columnar terminal portions include, as an outermost plating layer, a roughened silver plating layer having acicular projections. The roughened silver plating layer has a crystal structure in which the crystal direction &#x3c;101&#x3e; occupies a largest proportion among the crystal directions &#x3c;001&#x3e;, &#x3c;111&#x3e; and &#x3c;101&#x3e;. The substrate for mounting a semiconductor element thereon can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer, which are to serve as terminals and the like, to be thin.

A lead frame includes, as an outermost plating layer, a roughened silver plating layer having acicular projections and covering the entire surface of a lead frame substrate made of a copper-based material. The roughened silver plating layer has a crystal structure in which the crystal direction &#x3c;101&#x3e; occupies a largest proportion among the crystal directions &#x3c;001&#x3e;, &#x3c;111&#x3e;, and &#x3c;101&#x3e;. The lead frame can be manufactured with improved productivity owing to reduction in cost and operation time, and achieves remarkably high adhesion to sealing resin while keeping the total thickness of plating layers including the silver plating layer to be thin.

A multi-row wiring member configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in a bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed in the resin layer on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a metal frame is formed at a margin around an aggregate of individual wiring members arrayed in the matrix.

Multi-row wiring member for semiconductor device and method for manufacturing the same

A lead frame includes a plurality of leads formed from a metal plate having a front side and a back side, a first resin member, and a second resin member. The leads have side faces thereof fixed with the first resin member. Faces serving as internal connectors of the leads are uncovered on the side of the front-side surface of the first resin member, and faces serving as external connectors of the leads are uncovered on the side of the back-side surface of the first resin member. The second resin member is formed on the front-side surface of the first resin member to be at a level higher than the faces serving as the internal connectors, and has openings for leaving the faces serving as the internal connectors uncovered.

A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a permanent resist, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the permanent resist with lower faces thereof uncovered in the bottom surface of the permanent resist. The plating layer forming wiring portions is formed on the first plating layer in the permanent resist. The second plating layer is formed in the permanent resist on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the permanent resist. On a bottom-surface side of the permanent resist, a metal frame is formed at the margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix.

A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in the bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a resin frame is integrally formed with the resin layer at the margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix.

A multi-row LED wiring member includes a first plating layer, a second plating layer and a resin layer, to form individual wiring members arrayed in a matrix. In each wiring member, the first plating layer and the second plating layer constitute a laminated piece to form a pad portion and a laminated piece to form a lead portion. A first surface of the first plating layer is uncovered on a first-surface side of the resin layer. The second plating layer is formed on a part of a second surface of the first plating layer as being uncovered on a second-surface side of the resin layer. The laminated pieces substantially have a T-shape or L-shape as viewed from a lateral side. The first surface of the first plating layer is a surface of an Ag plating layer formed by removal of a metal plate, to maintain a good reflectance without brightener.

Multi-row LED wiring member and method for manufacturing the same

Methods for producing a substrate for semiconductor element mounts are provided. A base substrate can be prepared having on a first metal layer, a second metal layer through which a metal layer for instrumentation is hardly diffusible. A patterned resist mask layer on the second metal layer can be formed. A surface of the second metal layer under reprocessing treatment can form a reprocessed surface which can be provided with an organic film that controls adhesion between the metal layer for instrumentation and the reprocessed surface by a liquid agent containing a component that shows the nature of amphoteric surfactant. The metal layer for instrumentation can be formed on the reprocessed surface via the organic film. A semiconductor element mount portion and an electrode terminal portion can be electroformed on the metal layer for instrumentation. The resist mask from the second metal layer of the base substrate may be removed.

Method for producing substrate for mounting semiconductor element

A metal plateto be a lead frame has a plating with Sn or Zn or a plating with various alloys containing these metals only on the side faces and half-etched faces, and a noble metal plating layer formed on the front surface as a surface on which a semiconductor device is to be mounted.

Lead frame and method for manufacturing the same

A semiconductor lead frame includes a metal plate and a semiconductor chip mounting area provided on a top surface of the metal plate. A first plating layer for an internal terminal is provided around the semiconductor chip mounting area. A second plating layer for an external terminal is provided on a back surface of the metal plate at a location opposite to the semiconductor chip mounting area. The first plating layer includes a fall-off prevention structure for preventing the first plating layer from falling off from an encapsulating resin when the top surface of the metal plate is encapsulated in the encapsulating resin. The second plating layer does not include the fall-off prevention structure.

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Isa, Japan

Kaoru Hishiki