Texas Instruments Corporation

Kaoru Awaka

Hiroshi Takahashi

Yutaka Toyonoh

Akihiro Takegama

Tsuyoshi Tanaka

Rimon Ikeno

Masashi Hashimoto

Masaaki Aoki

Osamu Handa

Shigetoshi Muramatsu

A multiply-accumulate module () includes a multiply-accumulate core (), which includes a plurality of Booth encoder cells (). The multiply-accumulate core () also includes a plurality of Booth decoder cells () connected to at least one of the Booth encoder cells () and a plurality of Wallace tree cells () connected to at least one of the Booth decoder cells (). Moreover, at least one first Wallace tree cell () or at least one first Booth decoder cell (), or any combination thereof, includes a first plurality of transistors, and at least one second Wallace tree cell () or at least one second Booth decoder cell (), or any combination thereof, includes a second plurality of transistors. In addition, at least one critical path of the multiply-accumulate module () includes the at least one first cell and a width of at least one of the first plurality of transistors is greater than a width of at least one of the second plurality of transistors.

Multiply-accumulate modules and parallel multipliers and methods of designing multiply-accumulate modules and parallel multipliers

A compressor of a multiplier according to an embodiment of the present invention includes a first compressor, in which the first compressor includes a first plurality of inputs. The first compressor also includes a summation output, a first carry bit output; and a first plurality of transistor paths connecting each of the first plurality of inputs to the summation output. The compressor also includes a successive compressor, in which the successive compressor includes a second plurality of inputs and a plurality of successive transistor paths connecting at least one of the first plurality of inputs to the first carry bit output and connecting the first carry bit output to at least one of the second plurality of inputs. In one embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than seven and a successive compressor critical transistor stage path level within the successive compressor is less than eight. In another embodiment of the present invention, a first compressor critical transistor stage path level within the first compressor is less than eight and a successive compressor critical transistor stage path level within the successive compressor is less than seven.

4-2 compressor

4-2 Compressor

A semiconductor integrated circuit wherein the circuit area can be minimized, and defects can be detected reliably during a standby status while maintaining the reliability of a gate oxide film. Switching circuitis provided between logic circuitand source voltage Vsupply terminal. While in an operating status, 0 V voltage is applied to the gate of transistor MPof switching circuitand bias voltage Vequal to or slightly lower than source voltage Vis applied to its channel region in order to reduce the threshold voltage of transistor MPand increase its current driving capability. While in a standby status, a voltage equal to source voltage Vis applied to the gate of transistor MP, a voltage lower than the source voltage is applied to the source, and bulk bias voltage Vequal to or higher than source voltage Vis applied to the channel region in order to minimize the drain current of transistor MP, so that current path of logic circuitis cut off, and the occurrence of leakage current is suppressed.

Suppressing the leakage current in an integrated circuit

This invention describes circuit techniques providing a means for achieving reliable data retention and low leakage current in single step latches with switch transistors. The techniques require changes only in the circuit configuration. Neither higher cost technology such as multiple-threshold LVT/HVT transistors nor special control circuits are needed.

Low leakage single-step latch circuit

A semiconductor circuit which can restrain increase in manufacturing cost and layout area to a minimum level and can realize high speed and low power consumption. Bias voltages with different levels are generated corresponding to a mode control signal by a bias voltage supply circuit comprising PMOS transistors P and P which have different voltages applied to the respective sources and the mode control signal input to the gates. The generated bias voltages are supplied to the n-wells of PMOS transistors. During operation, a bias voltage that is almost the same as the operation voltage is applied to the n-wells of PMOS transistors. During standby, a bias voltage higher than the operation voltage is supplied to the aforementioned n-wells of PMOS transistors. In this way, the driving currents of the transistors can be kept at a high level during operation, while leakage currents of the transistors can be restrained during standby. Consequently, high speed and low power consumption can be realized.

High speed semiconductor circuit having low power consumption

The objective of this invention is to provide a type of semiconductor integrated circuit which can lessen solution in the circuit area to the minimum necessary level, and can lessen the leakage current in the standby state so as to cut the power consumption, and which allows I test to determine whether it is passed or defective. Logic circuit composed of low threshold voltage transistors and switching circuit composed of transistors having the standard threshold voltage are set. In the operation, the switching circuit is turned ON, and a driving current is fed to logic circuit . On the other hand, in the standby mode, the switching circuit is turned OFF, and the path of the leakage current is cut off to lessen generation of the leakage current. In the case of I test, different bulk bias voltages are applied to the channel regions of PMOS transistors and NMOS transistors from an IC tester through pads P and P . In this way, the leakage current can be lessened on a low level, and whether the semiconductor integrated circuit is passed or defective can be judged from the results of the current measurement.

Semiconductor integrated circuit

A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.

Growing community of inventors

Ibaraki, Japan

Kaoru Awaka