Hitachi, Ltd.

Kaori Nakayama

Takahiko Kozaki

Takayuki Kanno

Mitsuhiro Wada

Yusho Futami

Nobuyuki Yamamoto

Akihiko Takase

Masahiro Takatori

Norihiko Moriwaki

Masaru Murakami

Makoto Matsuoka

Masami Takahashi

Takaaki Toyama

Masumi Fukano

Akio Makimoto

Hitoshi Yajima

Yasuo Oginuma

A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.

Shared buffer type variable length packet switch

A packet switch which includes input line interfaces for converting variable length packets received from input lines to fixed length cells, a switch unit for switching said packets in cell units, output line interfaces for converting output cells from the switching unit to variable length packets and transmitting the variable length packets over output lines. Each of the input line interfaces has a cell output controller for queuing the fixed length cells for each output line according to the degree of priority of the cells, and for selectively outputting the stored cells in the queues in order of priority, thereby to suppress the transmission of cells with a low priority during the times of congestion.

Packet switch for switching variable length packets in the form of ATM cells

For reducing the scale of a multiplexer, a lower speed ATM interface block, an interface block for SDT mode circuit emulation, and an interface block for UDT mode circuit emulation perform processing for terminating services provided by lower speed transmission lines accommodated therein, and part of AAL processing, which is pre-processing depending on a service, for generating ATM cells from signals received by a terminated service, and send the processed signal to a higher speed line interface using a previously assigned time slot on a time-division bus. The higher speed line interface once stores the signals received from the time-division bus in a buffer, and subsequently performs certain processing including a common portion for respective signals for generating therefrom ATM cells in which the signals are stored in payloads. The generated ATM cells are multiplexed and transmitted onto a higher speed transmission line.

Multiplexing apparatus for transit of signals between service provided

Growing community of inventors

Yokohama, Japan

Kaori Nakayama