Taiwan Semiconductor Manufacturing Comp. Ltd.

Kaochao Chen

Ming Chyi Liu

Chia-Cheng Ho

Yuan-Sheng Huang

The present disclosure relates a method of manufacturing an integrated chip structure. The method forms an intermediate first material layer over a substrate and an intermediate second material layer on the intermediate first material layer. The intermediate second material layer is patterned to form an insulating layer. The intermediate first material layer is patterned to form a first material layer having an outermost sidewall indented inward from an outermost sidewall of the insulating layer. An ion bombardment process is performed on the insulating layer to dislodge one or more atoms from the insulating layer. A re-deposition process is performed to re-deposit the one or more atoms onto the outermost sidewall of the first material layer and to form a self-filling spacer below the insulating layer.

Self-filling spacer structure

An integrated chip includes a gate structure overlying a substrate between a source region and a drain region. A field plate is disposed within a first dielectric layer overlying the substrate. The field plate is laterally offset from the gate structure by a non-zero distance in a direction towards the drain region. An isolation structure is disposed within the substrate. The field plate directly overlies at least a portion of the isolation structure.

Field plate and isolation structure for high voltage device

Some implementations described herein provide techniques and apparatuses for forming a semiconductor device including a metal-insulator-metal capacitor. The metal-insulator-metal capacitor includes a dielectric pad layer having a portion between a capacitor bottom metal electrode layer and a portion of an insulator layer. The dielectric pad layer may preserve a thickness of the insulator layer to reduce a likelihood of a leakage between a capacitor top metal electrode layer and the capacitor bottom metal electrode layer. The dielectric pad layer may also enable a reduction in a thickness of the insulator layer to increase a capacitance of the metal-insulator-metal capacitor.

Metal-insulator-metal capacitor including a dielectric pad layer and providing a high capacitance a low leakage current

An integrated chip includes a field plate overlying an isolation structure. A gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an upper surface of the gate electrode to a front-side of the substrate. The etch stop layer overlies a drift region disposed between the source region and the drain region. The field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front-side of the substrate to a point below the front-side of the substrate. The isolation structure is disposed laterally between the gate electrode and the drain region.

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Hsin-Chu, Taiwan

Kaochao Chen