Winbond Electronics Corporation

Kao-Tsair Tsai

Chun-Hung Lin

Li-Ming Wang

Yen-Jui Chu

Min-Hung Chen

Yu-Cheng Tung

Bo-Lun Wu

Yao-Ting Tsai

Ting-Ying Shen

Hsin-Hung Chou

Chung-Hsien Liu

Tsung-Wei Lin

Tz-Hau Guo

Chun-Sheng Wu

Kun-Che Wu

Chii-Ming Shiah

Chao-Yi Huang

Tso-Hua Hung

Chun-Yen Liao

Chien-Hsien Wu

Jan-Nan Oue

Yasuko Tabata

Li-Mimg Wang

Tung-Yu Wu

Chang-Ju Ho

Hsaio-Yu Lin

Ying-Hao Chen

A method for forming a semiconductor memory structure includes sequentially forming an active layer, a hard mask layer and a core layer over a substrate, and etching the core layer to form a core pattern. The core pattern includes a first strip, a second strip, and a plurality of supporting features abutting the first and second strips. The method also includes forming a spacer layer alongside the core pattern, removing the core pattern, forming a photoresist pattern above the spacer layer, etching the hard mask layer using the photoresist pattern and the spacer layer to form a hard mask pattern, and transferring the hard mask pattern into the active layer to form a gate stack.

Method for forming semiconductor memory structure

A manufacturing method for a semiconductor structure is provided. First active areas, a second active area, and a third active area are formed. A first dielectric layer is formed on the active areas. A patterned region that includes a cavity region and a dielectric region is formed in the first dielectric layer, and the cavity region surrounds the dielectric region. A filling layer is formed in the cavity region. Multiple first contact holes and at least one second contact hole that penetrate the first dielectric layer are formed. Each first contact hole exposes a portion of the corresponding first active area, and the second contact hole replaces the dielectric region and exposes a portion of the second active area. Metal layers are filled in to the first contact holes and the second contact hole.

Semiconductor structure and manufacturing method of the same

A method for manufacturing a semiconductor device includes forming a metal layer in a substrate and sequentially forming a barrier layer and an insulating layer on the substrate. The method includes performing a first etching step to form an opening in the insulating layer, and the opening does not expose the barrier layer. After the first etching step, a gap-filling layer is formed on the insulating layer and fills the opening. The method includes performing a second etching step to form a first via communicating with the opening in the gap-filling layer, and an upper portion of the opening is widened to form a trench. The method includes performing a third etching step to remove the gap-filling layer in a bottom of the opening and to deepen both the trench and the opening. The method includes forming a second via communicating with the opening to expose the metal layer.

Method for manufacturing semiconductor device

A method for manufacturing a non-volatile memory device is provided. The method includes forming a trench through a sacrificial layer and extending into a substrate, filling a first insulating material into the trench, and implanting a dopant in the first insulating material by an implantation process. Then, the first insulating material is partially removed to form a first recess between the sacrificial layers. The lowest point of the first recess is lower than the top surface of the substrate. The method includes filling a second insulating material in the first recess and removing the sacrificial layer to form a second recess adjacent to the second insulating material. The method includes forming a first polycrystalline silicon layer in the second recess, and sequentially forming a dielectric layer and a second polycrystalline silicon layer on the first polycrystalline silicon layer.

Method for manufacturing non-volatile memory device

An image analysis method is provided. In the image analysis method, a to-be analyzed image is inputted into a region-based convolutional neural network (RCNN) model to obtain a masked image outputted from the RCNN. The center of a masked object in the masked image is calculated. The center is regarded as an origin of coordinate and the farthest coordinate point from the origin of coordinate in each of the four quadrants relative to the origin of coordinate are searched. The image analysis block is generated for each of the farthest coordinate points. The post-processing is performed on the image analysis blocks to obtain an object range.

Image analysis system and image analysis method for obtaining object range

A semiconductor device is provided and includes a first pad and a second pad, a first conductive connector and a second conductive connector, a first conductive structure and a second conductive structure. The first conductive connector and the second conductive connector are disposed over the first pad and the second pad. The first conductive structure is electrically connected to the first pad and the first conductive connector, and includes a first portion, a second portion and a connecting portion connecting the first and second portions. The first portion and the second portion are not overlapped in a vertical direction, and the first portion, the connecting portion and the second portion are integrally formed. The second conductive structure is electrically connected to the second pad and the second conductive connector, wherein a portion of the second conductive structure is overlapped with the first conductive structure therebeneath in the vertical direction.

Semiconductor device including conductive structure

A method of forming semiconductor devices includes providing a substrate with a patterned material layer formed thereon, forming a material layer on the patterned material layer, wherein the material layer has a first region with a lower top surface and a second region with a higher top surface, forming a flowable material layer on the material layer, wherein the flowable material layer exposes at least a portion of the second region of the material layer, removing the exposed portion of the second region of the material layer with the flowable material layer as a stop layer, removing the flowable material layer, and planarizing the material layer.

Methods of forming semiconductor devices with flowable material for better planarization method

Memory devices are provided. The memory device includes a substrate. A dielectric layer is disposed on the substrate and a plurality of resistive memory cells is disposed on the dielectric layer. Each resistive memory cell includes a via disposed in a first opening of the dielectric layer. A conductive layer is disposed on the via. The memory device further includes a capacitor structure including a bottom electrode, a variable resistance layer disposed on the bottom electrode and a top electrode disposed on the variable resistance layer, wherein the bottom electrode is disposed on the conductive layer.

Memory devices

An overlay mark applicable in a non-volatile memory includes two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, two second Y-direction isolation structures, a first dielectric layer, and a conductive layer. The first X-direction isolation structures, the first Y-direction isolation structures, the second X-direction isolation structures, and the second Y-direction isolation structures are disposed in a substrate. The first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle, and the second rectangle is located in the first rectangle. The first dielectric layer is disposed on a surface of the substrate. The conductive layer is disposed on the first dielectric layer.

Overlay mark

A method of manufacturing an overlay mark is provided. Two first X-direction isolation structures, two first Y-direction isolation structures, two second X-direction isolation structures, and two second Y-direction isolation structures are formed in a substrate, where the first X-direction isolation structures and the first Y-direction isolation structures are arranged to a first rectangle, and the second X-direction isolation structures and the second Y-direction isolation structures are arranged to a second rectangle. The second rectangle is located in the first rectangle. A first dielectric layer and a conductive layer are formed sequentially on the substrate. A planarization process is performed to remove a portion of the conductive layer till the isolation structures are exposed. A second dielectric layer is formed on the substrate. A rectangle pattern is formed on the second dielectric layer. The sides of the rectangle pattern are located above the isolation structures.

Method of manufacturing an overlay mark

An immersion lithography process is described. First, a photoresist layer on a material layer is formed. Then, an acid compensation layer is formed on the photoresist layer. An immersion exposure step is performed on the acid compensation layer and the photoresist layer. The acid compensation layer contains a photo-acid generator with a concentration of the photo-acid higher than that produced by a photo-acid generator in the photoresist layer after the immersion exposure step. Then, a development step is performed to pattern the acid compensation layer and the photoresist layer.

Immersion lithography process, and structure used for the same and patterning process

First of all, a substrate applied in the lithography process is provided, and then a high transmission attenuate layer (HTAL) is formed on the substrate. Then an opaque layer is formed on the high transmission attenuate layer (HTAL), and then an ion-implanting process is performed in the high transmission attenuate layer (HTAL). Afterward, the opaque layer is etched to define a first phase region and a second phase region on the high transmission attenuate layer (HTAL). Subsequently, a photoresist layer is formed on the second phase region and the opaque layer to expose a partial surface of the high transmission attenuate layer (HTAL) that is located the first phase region. Then the partial surface of the high transmission attenuate layer (HTAL) that is located on the first phase region is etched through until a predetermined depth in the substrate. Finally, removing the photoresist layer is to form a phase shifted region in the etched region and a phase unshifted region in the unetched region, whereby a phase mask that can make uniform exposure intensity is obtained by this invention.

Method for fabricating phase mask of photolithography process

A semiconductor apparatus and method for upgrading uniformity of critical dimension by compensating the flare effect at wafer edge are disclosed. In one embodiment of the invention, the invention uses an exposure plate mounted on tilt pincettes which can protrude and retract from a wafer stage of a stepper to eliminate the alteration of uniformity of critical dimension at wafer edge. The exposure plate uses the tilt pincettes to tilt along with a wafer so as to keep planar with the wafer.

Semiconductor manufacturing apparatus and method

A photomask set and a photolithographic operation suitable for forming a desired pattern on a photoresist layer. The photomask set includes a plurality of photomasks each having a different pattern thereon. To form an overall pattern on the photoresist layer, each photomask is used in turn in a multi-exposure operation.

Photomask set for photolithographic operation

A multilayer photoresist process in photolithography, which is applicable on a substrate having a composite photoresist layer with a desired thickness formed thereon. The present invention provides a process, comprising the following steps. A photoresist layer is formed on a substrate, and subsequently exposed through a photomask, followed by the developing process to pattern the photoresist. Then, the patterned photoresist layer is stabilized. This sequence is repeated untill at least another one layer is deposited and patterned on the substrate. Each photoresist layer has almost the same pattern with the underlying patterned photoresist layer. Many thin photoresist layers are accumulated to form a composite photoresist layer with a desired thickness.

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Kaohsiung, Taiwan

Kao-Tsair Tsai