Taiwan Semiconductor Manufacturing Comp. Ltd.

Kao-Chao Lin

Chia-Ta Hsieh

Chi-Wei Ho

Chen-Ming Huang

Po-Kai Hsu

Josh Lin

Shih-Jung Tu

Nai-Chao Su

Shih-Ching Lee

Kuo-Chyuan Tzeng

Chang-Chih Huang

Yu-Ting Tsai

Tsung-Hua Yang

Ching-Tzer Weng

Yi-Tzu Lin

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first gate electrode disposed on the substrate and located in a first region of the semiconductor device. The semiconductor device also includes a first sidewall structure covering the first gate electrode. The semiconductor device further includes a protective layer disposed between the first gate electrode and the first sidewall structure. In addition, the semiconductor device includes a second gate electrode disposed on the substrate and located in a second region of the semiconductor device. The semiconductor device also includes a second sidewall structure covering a lateral surface of the second gate electrode.

Semiconductor device and method of manufacturing the same

A device includes a first plurality of conductive strips have lengthwise directions in a first direction, a selector array overlapping the first plurality of conductive strips, an electrode array overlapping the selector array, a plurality of memory strips over the electrode array, and a second plurality of conductive strips overlapping the plurality of memory strips. The plurality of memory strips and the second plurality of conductive strips have lengthwise directions in a second direction perpendicular to the first direction.

Memory arrays including continuous line-shaped random access memory strips and method forming same

A flash memory device is disposed on a semiconductor substrate. The flash memory device includes flash memory cells arranged in rows and columns. Respective flash memory cells include respective access transistors and respective floating gate transistors. The respective access transistors have respective access gates, and the respective floating gate transistors have respective control gates arranged over respective floating gates. First and second wordlines extend substantially in parallel with one another and correspond to first and second rows which neighbor one another. The first wordline is coupled to access gates of access transistors along the first row. The second wordline is coupled to access gates of access transistors along the second row. Nearest edges of the first and second wordlines include at least one wing which extends laterally outward from a sidewall of one of the first and second wordlines towards a sidewall the other of the first and second wordlines.

Wing-type projection between neighboring access transistors in memory devices

Growing community of inventors

Fanlu Township, Taiwan

Kao-Chao Lin