Huawei Technologies Co., Limited

Tsinghua University

Kanwen Wang

Qi Liu

Shihai Xiao

Rui Zhang

Chuanzeng Liang

Wei Wu

Bin Gao

Wei Yang

Xing Hu

Huaqiang Wu

Tieying Wang

Peng Yao

Jianxing Liao

Leibin Ni

Junren Chen

A unit includes a first transistor, a memristor, and a resistance modulation unit, where a first port of the resistance modulation unit and a first port of the memristor are coupled to a first electrode of the first transistor, and the first electrode of the first transistor is configured to control the first transistor to be coupled and decoupled. The resistance modulation unit is configured to adjust, based on a resistance of the memristor, a voltage applied to the first electrode of the first transistor. The resistance of the memristor indicates the first data stored by the memristor, and when a voltage indicating second data is input to a second electrode of the first transistor which is configured to output a computation result of the first data and the second data from a third electrode of the first transistor.

Changing resistance of modulation system with changing resistance of memristor to output computation result

A storage device may be used in a neural network. The storage device includes a memristor unit, a current-controlled circuit, and a write circuit. The memristor unit has a structure of one-transistor and one-resistive random access memory (1T1R). The current-controlled circuit is configured to limit a current passing through the memristor unit to a target current, where the target current is determined based on target conductance of the memristor unit and a gate voltage of the transistor, and the target conductance is used to indicate target data to be written into the memristor unit. The write circuit is configured to load a write voltage to the memristor unit in cooperation with the current-controlled circuit, to write the target data to the memristor unit.

Storage device and data writing method

A memory refresh method is applied to a computer system including a processor, a memory controller, and a dynamic random access memory (DRAM). The memory controller receives a first plurality of access requests from the processor. The memory controller refreshes a first rank in a plurality of ranks at shortened interval set to T/N when a quantity of target ranks to be accessed by the first plurality of access requests is less than a first threshold and a proportion of read requests in the first plurality of access requests or a proportion of write requests in the first plurality of access requests is greater than a second threshold. T is a standard average refresh interval, and N is greater than 1. The memory refresh technology provided in this application can improve performance of the computer system in a memory refresh process.

Memory refresh technology and computer system

A memory allocation method and a device, where the method is applied to a computer system including a processor and a memory, and comprises, after receiving a memory access request carrying a to-be-accessed virtual address and determining that no memory page has been allocated to the virtual address, the processor selecting a target rank group from at least two rank groups of the memory based on access traffic of the rank groups. The processor selects, from idle memory pages, a to-be-allocated memory page for the virtual address, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.

Allocation of memory ranks based on access traffic

Growing community of inventors

Hangzhou, China

Kanwen Wang