Harris Corporation

Intersil Americas Inc.

Intersil Corporation

Other

Kantilal Bacrania

Gregory J Fisher

Chong I Chi

Mario Sanchez

Bang-Sup Song

J Mikko Hakkarainen

Hsin-Shu Chen

Eric C Sung

Michael D Church

Akira Ito

Brian L Allen

Tzi-Hsiung Shu

Choong-Sun Rhee

Jeffrey Michael Johnston

Glenn Alan DeJong

John T Gasner

Bruce J Tesch

Renyuan Huang

Glenn A Dejong

Shen Tu

Dave Kutchmarick

Jeffrey M Johnston

A dual pump circuit including a transmission gate and a dual charge pump. The transmission gate includes a p-channel transistor and an n-channel transistor, each having a control terminal and a pair of current terminals coupled between a dual pump input and a dual pump output. The dual charge pump includes first and second pump circuits, where each pump circuit is coupled to the dual pump input and to a control terminal of a corresponding one of the transmission gate transistors. Each pump circuit is operative to linearize operation of its corresponding transmission gate transistor by maintaining VGS&mdash;VT constant. The dual pump circuit is used in a track and hold circuit including at least one dual pump sampling circuit, at least one sampling capacitor, and a control circuit for controlling input signal sampling timing. Each dual pump sampling circuit includes the transmission gate and a dual charge pump.

Track and hold with dual pump circuit

A compensation system for calibrating an amplifier having a compensation input including a sigma delta converter, a counter, a memory, adjust logic, a DAC, a pair of compensation capacitors, and a pair of current to voltage (I/V) converters. The converter converts an offset voltage to a bit stream. The counter stores a sum value indicative of the output offset. The memory stores a digital bias value. The adjust logic determines an adjust value based on the sum value and adjusts the stored digital bias value based on the adjust value. The DAC converts the digital bias value to a differential bias current. The compensation capacitors apply a compensation voltage to a compensation input of the amplifier. The I/V converters charge the compensation capacitors using the differential bias current. The adjust logic may use upper and lower thresholds and adjust the digital bias value by one LSB for each compensation cycle.

System and method of DC calibration of amplifiers

A calibration system and method for a resistor ladder that employs relative measurement and adjustment between pairs of resistors. The system includes a resistor tree of complementary pairs of programmable resistors coupled to the resistor ladder, a measurement circuit that measures voltage differences between complementary pairs of programmable resistors, and control logic. The control logic controls the measurement circuit to measure a voltage difference between each complementary pair of programmable resistors and adjusts the relative resistance of each complementary pair of programmable resistors to equalize voltage. The measurement is facilitated by a sigma-delta ADC that converts a measured voltage difference into a bit stream. The programmable resistors are implemented with binary weighted resistors that are digitally adjusted one LSB at a time. Lower and upper adjustment thresholds may be employed to avoid unnecessary over-adjustments while maintaining a requisite level of accuracy.

Calibration of resistor ladder using difference measurement and parallel resistive correction

A multistage ADC that subranges and interpolates, and that amplifies selected subranges to convert an analog signal to a stream of digital values. The ADC samples the analog signal and provides a stream of sample signals. A first stage flash converts each sample signal into a first multiple bit value and subranges a reference ladder according to the first multiple bit value into selected reference signals. Each additional secondary stage amplifies a selected subrange of signals from a prior stage, flash converts the amplified residual signals to provide an additional multiple bit value, interpolates each set of amplified residual signals and subranges the interpolated signals according to the corresponding multiple bit value. A final stage amplifies and flash converts to determine a final multiple bit value. An error corrector combines each set of multiple bit values into a digital value.

Analog to digital converter using subranging and interpolation

An integrated circuit has an isolation structure in the form of a double diode moat. The P substrate has P&plus; buried layers,and,on opposite sides of N&plus; buried layer,. Analog devices are formed behind one diode moat, digital CMOS devices are formed behind the other moat.

Analog-to-digital converter and method of fabrication

A digital-to-analog converter (DAC) includes a plurality of current sources on a substrate operable in a predetermined sequence of use for generating an output current based upon a digital input, and a connection network for establishing the predetermined sequence of use for the current sources based upon the actual current values and to increase performance of the DAC. For example, the predetermined sequence of use can be set to reduce integral non-linearity error of the DAC. The connection network may be provided by a plurality of fusible links selectively connected to set the predetermined sequence of use. The current sources may include a first group of most significant bit (MSB) current sources for a predetermined number of MSBs. In addition, the plurality of current sources may include a second group of mid-most significant bit (mid MSBs) current sources for a predetermined number of mid MSBs. The plurality of current sources have actual values sortable from lowest to highest, and each actual current value will define an error value with both a magnitude and polarity relative to the desired value. One embodiment for sorting the order of use of the current sources is based upon the error values.

Digital-to-analog converter including current sources operable in a

An analog-to-digital converter (ADC) includes a plurality of capacitors formed on a semiconductor substrate and having actual capacitance values statistically related to desired capacitance values, and a gain stage comprising an amplifier and capacitors selected to provide a more accurate gain for the gain stage. A first at least one capacitor is connected between an input and an output of the amplifier defining a feedback capacitance, and a second at least one capacitor is connected between the input of the amplifier and an input of the at least one gain stage defining an input capacitance. In addition, the ADC includes a connection network selectively connecting the first at least one capacitor and the second at least one capacitor from among the plurality of capacitors to provide a desired ratio of feedback capacitance to input capacitance based upon the actual capacitance values. Accordingly, a gain can be set for the gain stage that is more accurate than would otherwise be obtained. The high accuracy switched capacitor gain stage may be used in other applications.

Analog-to-digital converter having enhanced accuracy gain stage, and

An integrated circuit has a pseudosubstrate 6060 with an isolation moat 9505. Substrate 6001 has one conductivity and a subcircuit region 6060 has an opposite conductivity. Digital CMOS devices are formed in the subcircuit over region 6060 and operate between zero to +5 volts. Analog devices are formed over the rest of the substrate and operate between plus and minus 5 volts. The moat 9505 isolates the digital CMOS devices from the analog devices.

A digital-to-analog converter (DAC) includes a first array of current source cells extending in first and second transverse directions, and a two-dimensional symmetrical controller for operating current source cells of the first array based upon at least a portion of digital input words and in a symmetrical sequence in both the first and second directions with respect to a medial position of the first array. The medial position preferably defines a centroid for the first array. The two-dimensional symmetrical controller may preferably include a decoder for generating a plurality of control signals based upon predetermined most significant bits (MSBs) of digital input words. Another aspect of the invention relates to the treatment of the LSBs. According to this aspect, the first array further comprises a plurality of second current source cells, and the two-dimensional symmetrical controller further operates the plurality of second current source cells based upon predetermined LSBs of digital input words. The DAC may include a substantially identical second array adjacent the first array. The two-dimensional symmetrical controller may operate the current source cells in the first and second arrays in pairs and in a substantially mirror image sequence to provide geometrical averaging. The geometrical averaging may operate the current source cells in the first and second arrays in pairs and in a substantially true mirror or inverted mirror image sequence.

Digital-to-analog converter including current cell matrix with enhanced

Then circuit includes an analog-to-digital converter (ADC); and one or more switched capacitor amplifier stages connected together in series with a first switched capacitor amplifier stage for receiving the analog input signal, and a last switched capacitor amplifier stage connected to the ADC. Moreover, each of the plurality of switched capacitor amplifier stages preferably has a selectable gain to permit control of an overall gain of the analog input signal upstream of the ADC. In addition, the first stage may also serve as a sample and hold circuit for the ADC. In one embodiment, the circuit may comprise an integrated circuit substrate on which the ADC and the plurality of switched capacitor amplifiers are formed so that the analog-to-digital converter is a monolithic integrated circuit. The circuit may also control the gain of each of the plurality of switched capacitor amplifier stages based upon a digital gain control word. A clock is preferably operatively connected to the ADC and the plurality of switched capacitor amplifier stages. Accordingly, gain control word changes cause relatively rapid changes in the overall gain.

Processor controlled analog-to-digital converter circuit

An analog-to-digital converter (ADC) integrated circuit includes a subconverter stage having an amplifier with a non-ideal gain, and a reference voltage generator for generating a reference voltage for the subconverter stage. The reference voltage generator is adjustable and may include trimmable resistors for providing an adjusted or trimmed reference voltage to a second subconverter stage or second operation of the subconverter stage to compensate for a non-ideal gain of the amplifier. Complicated and difficult capacitor trimming for the amplifier is not needed; rather, a relatively simple and predictable trimming of thin film resistors in the reference voltage generator may be used to compensate for the non-ideal gain of the amplifier and improve performance. A method and apparatus for calibrating the ADC are also disclosed.

Integrated circuit analog-to-digital converter and associated

Power monitoring circuit 5000 monitors a positive power supply Vcc and a negative power supply Vee. If either one or both power supplies fall below predetermined respective threshold values, a master reset pulse (MR) is generated. When both power supplies are at their normal operating level, the logic circuit 5040 generates a signal that enables operation of the circuit.

Integrated circuit with power monitor

The A-to-D converter 300 has an output buffer 320 with fourteen drivers each the same as driver 4100. Driver 4100 includes bipolar pull up pull down transistors 4102, 4103. Those transistors are both coupled to an output. Pull up transistor 4102 is coupled to a first reference voltage VDD; pull down transistor 4103 is coupled to a second or ground reference potential. A base drive circuit comprising a series connection between a resistor and a transistor 4121 to provide additional current to saturate the pull down transistor 4103 and thereby lower the collector-to-emitter voltage drop of transistor 4103 when transistor 4103 is turned on.

Analog-to-digital converter and output driver

An A-to-D converter 300 has a comparator 126 with a number of comparator cells 902. Each comparator cell 902 includes a current mirror 1700 that reduces kickback noise. Current mirror 1700 includes a bipolar current mirror 1705 and an NMOS current mirror 1709. The bipolar current mirror 1705 provides an ac ground paralleling NMOS transistor 1704 in the NMOS current mirror 1709 to reduce kickback noise.

Two stage current mirror

A BIMOS driver circuit and method in which a push-pull pair of PNP-NPN bipolar transistors replaces the middle CMOS inverter stages in a circuit for driving a capacitive load. The rise and fall times of the circuit are made symmetrical by feeding back driver circuit output to operate a feedback transistor which removes the base charge stored in a PNP transistor of the bipolar push-pull pair, and maintains low propagation delay.

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Palm Bay, FL, United States of America

Kantilal Bacrania