Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Other

Fuji Xerox Co., Ltd.

Tama-tlo Corporation

Kabushiki Kaisha Toshiba

Kyocera Corporation

Oki Electric Industry Co., Ltd.

Renesas Technology Corp.

Disco Corporation

Ibiden Company Limited

Fujitsu Microelectronics Limited

Vlsi Technology Research Association

Jjtech Co., Ltd.

Kanji Otsuka

Takayuki Okinaga

Kunizo Sahara

Yuuji Shirai

Yutaka Akiyama

Tamotsu Usami

Shigeo Kuroda

Hiroshi Akasaki

Yasuyuki Yamasaki

Hiroshi Tachi

Hisashi Nakamura

Yuji Shirai

Takashi Emata

Masao Sekibata

Michiaki Furukawa

Hiroshi Ozaki

Hiromichi Suzuki

Gen Murakami

Takashi Nakao

Akira Yamagiwa

Hitoshi Matsushima

Toshio Hatada

Satoru Ogihara

Masao Kawamura

Toshiyuki Sakuta

Hajime Hasebe

Ikuo Yoshida

Kazuya Ito

Akiomi Kohno

Masaya Horino

Hideaki Kamohara

Makoto Homma

Kazumichi Mitsusada

Takao Ohba

Osamu Horiuchi

Masanori Tazunoki

Yoshiaki Emoto

Tsuneo Ito

Toshihiko Satoh

Minoru Enomoto

Yuko Tanba

Hinoko Kurosawa

Shouji Matsugami

Masayuki Iketani

Koichiro Sekiguchi

Shouichi Irie

Keiji Sasaki

Hiromitsu Mishimagi

Fumio Mizuno

Munekazu Takano

Akira Tanaka

Takeo Yamada

Mitsuo Usami

Hiroshi Watanabe

Tadakatsu Nakajima

Kazuji Yamada

Katsuyuki Sato

Shigeo Ohashi

Hiroshi Inoue

Daisuke Iguchi

Tadahiko Miyoshi

Katsumi Ogiue

Motohiro Sato

Nobuyuki Ushifusa

Tetsuya Hayashida

Yoichi Sato

Heikichi Kuwahara

Kunio Miyazaki

Shunichi Numata

Tomoji Oishi

Hiroshi Inouye

Masao Sakuma

Osamu Miura

Hiromi Kagohara

Hironori Kodama

Masatoshi Tsuchiya

Masao Kato

Seiji Miyamoto

Takashi Kumagai

Shigeru Yamamoto

Yoshihiro Kondou

Yoshiyuki Ohzawa

Hisashi Ishida

Takeshi Koyama

Hiroshi Koguma

Toshihiro Tsuboi

Takashi Miwa

Shinji Ohnishi

Kunizou Sahara

Masahiro Yoshida

Yoshihiro Seimiya

Shinichi Shouji

Ai Mizuno

Saburo Yokokura

Kazutoshi Kubo

Masayuki Kawashima

According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area.

Multi chip semiconductor device

A circuit substrate is presented. The circuit substrate comprises internal terminal electrode; a substrate; a wiring layerformed on a portion of the surface of the substrate and having one end thereof connected to the internal terminal electrode; an insulating film contacting as a surface with the wiring layer; and an external terminal electrodeconnected to the other end of the wiring layer and used for connecting to the exterior. The angle of the cross-section of the wiring layer taken perpendicularly to the surface of the substrate in the edge portion that the wiring layer contains is 55&#xb0; (55 degree) or less, and the wiring layer that contains multiple mutually independent columnar crystals extending perpendicularly in a direction different from the direction of the surface of the substrate.

Circuit substrate and method of manufacturing same

A method of manufacturing a massive mixture of aluminum nitride and aluminum includes a first heat treatment process of manufacturing the massive mixture of aluminum nitride and aluminum by heating aluminum powder () and aluminum pieces () inserted into a vessel () at a temperature of a melting point of aluminum or higher under a nitrogen atmosphere. An oxide film is formed over the surface of the aluminum powder (). The oxide film is, for example, a natural oxide film. The weight ratio of the aluminum powder () to the aluminum pieces () is, for example, 0.1 or less.

Method of manufacturing massive mixture of aluminum nitride and aluminum

A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memoriesincluding basic cellsarranged in a cluster, the basic cellincluding a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memorieslocated along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibusincluding a through-via, an arbitrary one of the basic cellsis directly accessed through the multibusfrom the controller chip so that truth value data is written therein, and whereby the arbitrary basic cellis switched to a logic circuit as conjugate.

Memory/logic conjugate system

Disclosed is a semiconductor device wherein the switching speed of a transistor is increased. Specifically disclosed is a semiconductor device comprising a semiconductor layer formed on a part of an insulating layer, a first transistor formed on a lateral face of the semiconductor layer and having a first gate insulating film, a first gate electrode and two first impurity layers forming a source and a drain, and a second transistor formed on another lateral face of the semiconductor layer and having a second gate insulating film, a second gate electrode and two second impurity layers forming a source and a drain.

High-speed semiconductor device and method for manufacturing the same

A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside.

Semiconductor integrated circuit package, printed circuit board, semiconductor apparatus, and power supply wiring structure

The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnectionfor transmission of signals, a MOS capacitance elementhaving a gate electrode connected to the signal-transmission interconnection, a first voltage-applying interconnectionconnected to a source and a drain of the MOS capacitance elementand applying a voltage to the source and the drain of the MOS capacitance element, a second voltage-applying interconnectionconnected to a well of the MOS capacitance element, and applying a voltage to the well of said first MOS capacitance element. Jitters occurring in the signal-transmission interconnectioncan be adjusted by adjusting each of voltages of the first voltage-applying interconnectionand the second voltage-applying interconnection

Semiconductor device and method for adjusting characteristics thereof

An electronic device includes a wiring board, and at least one pair of signal lines that is provided on the wiring board in parallel and has an equal length. A chip is mounted on the wiring board and includes at least one differential driver which outputs complementary digital transmit signals to said at least one of lines. A pair of power system lines is provided to supply first and second power supply voltages to the above-mentioned at least one differential driver. The power system lines are parallel to each other and have an equal length.

Electronic device

In a semiconductor chip are arranged power pads, ground pads and signal pads. A ground line is provided which is formed as one in the vicinity of the chip and branches off at some distance from the chip. Signal lines and power lines are each formed over one of the branched ground lines. The signal lines and the power lines are extended radially together with the underlying ground lines. Each of the signal lines and the power lines are extended together with the corresponding ground line to form a stacked pair line.

Semiconductor circuit device having power and ground lines adapted for high-frequency operation

Signal wirings are formed on a pair of substrates and the substrates are joined together through an insulating layer so that the signal wirings are placed in parallel and facing to each other. The surfaces of the overlapping faces of the signal wirings are made smooth, and the roughness of the same surfaces is smaller than the skin depth &dgr; due to the skin effect, preferably less than one third, for minimizing the increase in the electric resistance due to the skin effect.

Wiring substrate and process for producing the same

A semiconductor circuit device includes a multi-layered substrate comprising a plurality of signal lines sandwiched between a power source line and a ground line, with insulation layers formed therebetween to reduce fluctuation of a ground line potential at the time of simultaneous switching of the signal lines and to increase the operational speed. The signal lines provides bidirectional current paths and is disposed between the current source line and the ground line. The multi-layered substrate is formed around a semiconductor pellet. Electrode pads are formed on the insulation layer over the ground line on the same level as the signal lines and generally on the same level as the main surface of the semiconductor pellet where electrodes pads are formed. Bonding wires are used to electrically connect the electrode pads on the pellet and the electrodes formed on the insulation layer. Additional bonding wires are used to electrically connect the electrode pads formed on the insulation layer and electrode pads formed on the power source line which is at a higher level and further away from the electrode pads formed on the insulation layer. Some of the electrode pads formed on the insulation layer is directly connected to the ground line using a side plate extension.

Semiconductor integrated circuit device

A cooling apparatus for an electronic device of high calorific density including an elastomer interposed between a semiconductor chip and a heat sink so as to connect them thermally. The elastomer may also be in close contact with a large number of semiconductor chips having various configurations which are mounted on a board, so that the elastomer is thermally connected with them, whereby the elastomer absorbs thermal deformations.

Cooling apparatus of electronic device

To achieve higher packaging density and one wafer level for a full-sized wafer memory, or wafer-scale integration memory system, the wafers are vertically stacked with each other at a predetermined interval. A packaging technique is improved in such a way that a memory system layout can be precisely realized and a precise through hole can be formed. Moreover, other chips are fixed on the wafer so as to achieve furthermore the high packaging density.

Wafer scale or full wafer memory system, packaging method thereof, and

A semiconductor device is provided having a semiconductor pellet that is arranged on a substantially central part of a film base in which a metal plate is overlaid with an insulating member, while inner leads are arranged on a peripheral part of the film base in a state in which they are electrically isolated from the metal plate of the film base. External terminals for a power source among external terminals of the semiconductor pellet and middle parts of the metal plate of the film base, as well as inner leads for the power source among the inner leads and peripheral parts of the metal plate are electrically connected by pieces of bonding wire, respectively.

Semiconductor device and method of producing the same

Growing community of inventors

Higashiyamato, Japan

Kanji Otsuka