Samsung Electronics Co., Ltd.

Chung Ang University Industry Academic Cooperation

Kangseok Lee

Geunyeong Yu

Hong Rak Son

Bohwan Jun

Hongrak Son

Dong-Min Shin

Youngjun Hwang

Hyunseung Han

Yongsung Kil

Soonyoung Kang

Heeyoul Kwak

Hee Youl Kwak

Dongmin Shin

Haesung Kwon

Seonghyeog Choi

Wijik Lee

Junho Shin

Jae Hun Jang

Dong-Eun Kim

Min Su Han

Nam Chul Ha

Wonchoul Yang

Ji Hyun Yeom

Maeng Je Seong

Sang Mi Ryou

Jeehyeon Bae

Disclosed is a method of operating a storage controller which is configured to communicate with a non-volatile memory device. The method includes receiving count data from the non-volatile memory device, determining a pre-read voltage based on the count data, sending a pre-read request using the pre-read voltage to the non-volatile memory device, receiving pre-read data from the non-volatile memory device responsive to sending the pre-read request, calculating a decoding value corresponding to the pre-read data, and generating read voltage information based on the count data and the decoding value, and the decoding value predicts an error voltage of the pre-read data.

Storage controller generating read voltages for soft decision decoding based on read information and decoding information, storage device including the same, and operating method thereof

Disclosed is a storage device which includes a nonvolatile memory device, and a memory controller that performs a read operation on the nonvolatile memory device and performs an error correction operation on data read in the read operation. In the error correction operation, the memory controller estimates an error rate of the read data, and determines whether to perform a read retry operation based on the estimated error rate.

Storage device performing error correction and operating method of storage device

In a method of error correction code (ECC) decoding, normal read data are read from a nonvolatile memory device based on normal read voltages, and a first ECC decoding is performed with respect to the normal read data. When the first ECC decoding results in failure, flip read data are read from the nonvolatile memory device based on flip read voltages corresponding to a flip range of a threshold voltage. Corrected read data are generated based on the flip read data by inverting error candidate bits included in the flip range among bits of the normal read data, and a second ECC decoding is performed with respect to the corrected read voltage. Error correction capability may be enhanced by retrying ECC decoding based on the corrected read data when ECC decoding based on the normal read data results in failure.

Method of error correction code (ECC) decoding and memory system performing the same

A low density parity check (LDPC) decoder initializing variable nodes with a value of a codeword and outputting the updated variable nodes as decoded messages with reference to an irregular parity check matrix. The LDPC decoder includes a plurality of unit logic circuits operating in a single mode in which all the unit logic circuits update one variable node group including at least one variable node, or a multi-mode in which each of the unit logic circuits updates a plurality of variable node groups in parallel by updating different variable nodes, and a mode controller controlling the plurality of unit logic circuits to update a high-degree variable node group having a degree greater than a threshold degree among the variable node groups in the single mode, and update a low-degree variable node group having a degree less than or equal to the threshold degree among the variable node groups in the multi-mode.

Low density parity check decoder and storage device

A method of responding to a read request from a host includes: obtaining read data from a memory device, performing first iteration ECC decoding on the read data to generate a plurality of pieces of decoded data, selecting one of the plurality of pieces of decoded data as intermediate data as intermediate data, generating preprocessed data based on the read data and the intermediate data and performing second iteration ECC decoding on the preprocessed data when the first iteration ECC decoding fails, and outputting the intermediate data to the host when the first iteration ECC decoding succeeds.

Error correction code engine performing ECC decoding, operation method thereof, and storage device including ECC engine

An error correction circuit includes a memory that stores at least one decoding parameter, a low density parity check (LDPC) decoder that includes a first variable node storing one bit of the data, receives the at least one decoding parameter from the memory, decides a degree of the first variable node based on the at least one decoding parameter, and decides a decoding rule necessary for decoding of the one bit based on the degree of the first variable node, and an adaptive decoding controller that outputs corrected data based on a decoding result of the LDPC decoder.

Error correction circuit and method for operating the same

An operating method of a storage controller which includes a high level decoder and a low level decoder includes generating first data that is a result of decoding initial data read from a nonvolatile memory device, and a first syndrome weight indicating an error level of the first data. The first data is output to a host when the first syndrome weight is a specific value. The high level decoder having a first error correction capability is selected to decode the first data, when the first syndrome weight exceeds a reference value, and the low level decoder having a second error correction capability lower than the first error correction capability is selected to decode the first data, when the first syndrome weight is the reference value or less.

Storage controller for correcting error, storage device including the same, and operating method thereof

The present invention provides a gene delivery system containing nanoparticles. In more detail, the present invention provides a gene delivery system containing (a) a nanomaterial; (b) an oligonucleotide as an universal binding partner covalently linked to the surface of the nanomaterial; and (c) a cargo comprising (i) a complementary oligonucleotide containing a nucleotide sequence complementary to the universal binding partner as a binding counter-partner, and (ii) an inhibitory molecule having a nucleotide sequence complementary to a target gene of interest to be inhibited or an inducible molecule having a nucleotide sequence of a target gene of interest to be expressed. The present invention is a gene delivery system capable of feasibly deliver aptamer, siRNA, shRNA, miRNA, ribozyme, DNAzyme, PNA or gene as well as antisense oligonucleotide into the cells. In addition, the present invention is more efficient than the commercially available gene transfer reagent in respect to the degree of knockdown of target protein expression.

Nanoparticle-based gene delivery systems

A method for detecting an asperity in a non-data parking zone of a disk in a hard disk drive. The method includes the steps of moving the heads of the disk drive adjacent to the parking zones of the disks, and then detecting asperities in the parking zones with a thermal asperity detection circuit.

Method for detecting mechanical damage in a parking zone of a hard disk drive

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Seoul, South Korea

Kangseok Lee