Broadcom Corporation

Kangmin Hu

Jun Cao

Afshin Momtaz

Ali Nazemi

Bo Zhang

Delong Cui

Burak Catli

Hyo Gyuem Rhew

Wayne Wah-Yuen Wong

A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Phase alignment architecture for ultra high-speed data path

A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.

High speed level shifter with amplitude servo loop

Growing community of inventors

Irvine, CA, United States of America

Kangmin Hu