Changxin Memory Technologies, Inc.

KangLing Ji

WeiBing Shang

Hongwen Li

Enpeng Gao

Zengquan Wu

Zhan Ying

Jun He

Kai Tian

Sungsoo Chi

Yuanyuan Gong

Daoxun Wu

Keqin Huang

Liang Zhang

Ying Chu Wang

Anping Qiu

Xianjun Wu

Fengqin Zhang

Chan Chen

Ying Wang

A memory includes: a memory cell array; a first column decoder, coupled to the memory cell array and configured to perform a write operation on the memory cell array; a second column decoder, coupled to the memory cell array and configured to perform a read operation on the memory cell array; and a read amplifier, the read amplifier and the second column decoder being located on two opposite sides of the memory cell array, the read amplifier being coupled to the memory cell array and configured to receive read data information output by the memory cell array based on the read operation. The read amplifier, the first column decoder, the memory cell array and the second column decoder are arranged in a first direction, and the first column decoder and the second column decoder are located on two opposite sides of the memory cell array.

Memory and operating method therefor

A timing sequence control circuit includes: a signal transmission module and a timing sequence compensation module, and the timing sequence compensation module is connected with the signal transmission module. Herein, the signal transmission module is configured to receive an initial sampling signal and transmit the initial sampling signal to generate a sampling signal. The timing sequence compensation module at least includes a compensation capacitor and is configured to receive an adjustable supply voltage, and perform compensation delay adjustment on the initial sampling signal according to the supply voltage and the compensation capacitor, so that the time difference between the sampling signal and a to-be-sampled Data (DQ) signal meets a preset requirement.

Timing sequence control circuit, timing sequence control method, and semiconductor memory

A memory is provided. The memory includes: a storage array that includes multiple bit lines, each of the multiple bit lines is connected to multiple storage cells in the storage array; multiple column select signal units that are connected to sensitive amplifiers, the sensitive amplifiers and the multiple bit lines are disposed in one-to-one correspondence; local data buses that are divided into local data buses O and local data buses E, adjacent bit lines are electrically connected to a respective local data bus O and a respective local data bus E, respectively, through a respective sensitive amplifier and a respective column select signal unit; and a first error checking and correcting unit and a second error checking and correcting unit that are configured to check and correct errors of data.

Memory with error checking and correcting unit

A data error correction circuit includes: a data error correction circuit, configured to receive first data and a first check code corresponding to the first data, perform error correction on the first data according to the first check code to generate second data, and output the second data; and a check code generation circuit, configured to receive the first data and the first check code, generate a second check code according to the first data and the first check code, and output the second check code.

Error correction circuit and data transmission method

A memory includes: a storage cell array; a write driver; and a first column decoder, the first column selection line includes a dummy route and a loaded route, the dummy route is coupled to the first column decoder and the loaded route and transmits a first column selection signal to the loaded route; the loaded route is coupled to a first storage cell area and transmits the first column selection signal to the first storage cell area; the first column selection signal selects a storage cell column, on which a write operation is performed, from the first storage cell area. A transmission direction of a data signal to be written transmitted by the write driver is identical to a transmission direction of the first column selection signal transmitted via the loaded route.

Memory and method of operation with dummy and loaded route

A voltage conversion circuit and a memory are provided. The voltage conversion circuit includes a driving circuit and a receiving circuit. The driving circuit is powered by a first voltage, and outputs a first signal at an output end, a voltage of a high level of the first signal being less than the first voltage. The receiving circuit is powered by the first voltage, receives the first signal at a first input end, and receives a sampling signal at a second input end. The receiving circuit is configured to output a second signal according to the sampling signal, and a voltage of a high level of the second signal is equal to the first voltage.

Voltage conversion circuit and memory

Provided are a data transmission circuit, a data transmission method, and a storage device. The data transmission circuit includes a controllable delay module and a mode register data processing unit. The controllable delay module is configured to generate a delayed read command in response to a mode register read command. The mode register data processing unit is configured to read setting parameters from a mode register in response to the mode register read command, and to output the setting parameters in response to the delayed read command. Here, a time difference between a start moment of outputting of the setting parameters and a moment when the controllable delay module receives the mode register read command is a first preset threshold.

Data transmission circuit, data transmission method and storage device

An address signal transmission circuit includes a transmission control circuit, connected to an address bus, configured to receive address signals from the address bus, acquire a first address signal and a second address signal, and generate and output an inversion flag signal based on the first address signal and the second address signal, where the first address signal is an address signal received in a previous time and the second address signal is a currently received address signal; and a selection circuit, connected to the address bus, configured to receive the address signals from the address bus, determine, in response to the inversion flag signal, whether the second address signal is to be inverted, and correspondingly output one of the second address signal or an address inverted signal, where the selection circuit inverts the second address signal to obtain the address inverted signal.

Address signal transmission circuit, address signal transmission method and storage system

A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where first input end is configured to receive high level signal, second input end is configured to receive low level signal, control ends are connected to selection unit and output end is connected to serial wire, and selection unit is configured to receive selection signal and at least two branch signals and configured to select, based on selection signal, one branch signal and transmit it to parallel branch; serial wire configured to organize signals output by parallel branches into serial signal; and drive units connected in parallel with each other and connected to serial wire for enhancing drive capability of serial wire, output ends of drive units being connected with each other and configured to output serial signal, and each drive unit being disposed adjacent to a respective parallel branch.

Parallel-to-serial conversion circuit, parallel-to-serial conversion circuit layout, and memory

This application relates to a data transmission circuit, a method making it, and a storage device. The circuit includes a mode register data storage unit and an array area data storage unit. The mode register data storage unit outputs mode register data in response to a first clock signal; the output terminal of the array area data storage unit and the output terminal of the mode register data storage unit are both connected to the first node, the array area data storage unit receives array area data in response to the first pointer signal, and outputs the array area data in response to the second pointer signal. This technic can accurately control the mode register data and the array area data to output through the respective output channels in turn.

Data transmission circuit, method of making it, and storage device

The present disclosure provides a signal line structure, a signal line driving method, and a signal line circuit. The signal line structure includes a plurality of parallel signal lines, where each of the signal lines is maintained in a drive state at any time.

Signal line structure, signal line driving method, and signal line circuit

A data transmission circuit and a data transmission method applied to the data transmission circuit are provided. The data transmission circuit includes: a data strobe module, connected to multiple memory blocks, connected to a low-bit data port through a first group of data buses, and connected to a high-bit data port through a second group of data buses, where each group of data buses include an odd data line and an even data line; and an error correction module, where each group of the data buses are provided with the error correction module, the error correction module is provided on the odd data line or the even data line, and the error correction module is configured to perform error correction on data written through the low-bit data port or the high-bit data port.

Data transmission circuit and data transmission method

A parallel-to-serial conversion circuit includes: parallel branches, each including first input end, second input end, control ends and output end, where the first input end is configured to receive high level signal, the second input end is configured to receive low level signal, the control ends are connected to selection unit and the output end is connected to a serial wire, and the selection unit is configured to receive selection signal and at least two branch signals, and is configured to select, based on the selection signal, one of the branch signals and transmit a selected branch signal to the parallel branch; the serial wire, configured to organize signals output by the parallel branches into a serial signal; and a drive unit, connected to the serial wire for enhancing drive capability of the serial wire, where an output end of the drive unit is configured to output the serial signal.

A storage system includes: a memory, configured to write or read a plurality of pieces of data during a read-write operation, the plurality of pieces of data being divided into M bytes, and each byte having N pieces of data; and an encoding circuit, configured to in the encoding stage, generate X first check codes based on the two or more pieces of data in each byte, generate Y second check codes based on all data of two or more bytes of the M bytes in the encoding stage, and generate a third check code based on the plurality of pieces of data, the X first check codes and the Y second check codes. The first check codes, the second check codes and the third check code are used to determine an error state of the plurality of pieces of data.

Storage system

A data error correction circuit and a data transmission circuit are disclosed. The data error correction circuit includes: a decoding circuit having an input terminal connected to a data bus, and configured to receive first data and a check code of the first data and output an error correction code of the first data based on the check code; and an error correction latch module having a first input terminal connected to the data bus and a second input terminal connected to an output terminal of the decoding circuit, and configured to latch the first data corresponding to the error correction code and generate and output second data according to the error correction code and the corresponding first data.

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Hefei, China

KangLing Ji