Apple Inc.

Sematech, Inc.

Oracle International Corporation

Kanghoon Jeon

Bilin Wang

Chun-Yao Huang

Tien-Chien Kuo

Ivan Knez

Yingkan Lin

Wei-Yip Loh

Hopil Bae

Jose Antonio Dominguez-Caballero

Brian Coss

Denis M Darmon

Mitchell Herman Kline

Stanley Bo-Ting Wang

Hoyeol Cho

Syed Farhan Mohiuddin

Pangjie Xu

Chanro Park

Jason T Su

A pixel circuit for an electronic display may include a memory to store a digital data signal indicative of a value within a data range. The pixel circuit may also include a light-emitting diode to emit light based at least in part on the digital data signal. The pixel circuit may also include an initialization transistor to initialize the pixel circuit before the light-emitting diode emits light and a driving transistor to activate based at least in part on the digital data signal.

Pixel circuitry and operation for memory-containing electronic display

A display system may include a memory external to a pixel that stores a first digital data value, a memory internal to the pixel that stores a second digital data signal, where a combination of the first digital data signal and the second digital data signal may indicate a target gray level assigned to the pixel for a particular image frame. The pixel may be driven for a first duration of time according to the first digital data signal and for a second duration of time according to the second digital data signal.

Dual-memory driving of an electronic display

A device may include an electronic display to display image frames. The display may include illuminators that generate light and mirrors that selectively direct the light to pixel locations based bitplanes that set the arrangement of the mirrors. Additionally, the device may include duty cycle balancing circuitry that generates and provides duty cycle balancing signals to the electronic display. In response to the duty cycle balancing signals, the electronic display is implements balancing on bitplanes during at least a first portion of off periods during the image frames and implements balancing off bitplanes during at least a second portion of the off periods such that, in the aggregate, a ratio of respective on times of the mirrors to respective off times of the mirrors is balanced across the image frames during the off periods.

Reflective display mirror hinge memory reduction systems and methods

Efficiently transmitting image data to an electronic display may be provided by skipping regions of the electronic display that display a default value. The electronic display may include a number of pixels, a row driver, and a data driver. The row driver may activate a first subset of the pixels for programming. The data driver may program a default pixel value to respective pixels of the first subset of the pixels for which image data has not been received and may program image data to respective pixels of the first subset of the pixels for which image data has been received.

Image data skipping for transmission to electronic display

An electronic display may include an active area having a first pixel formed in the active area, where the first pixel emits light in response to image data. The electronic display may also include a controller to transmit the image data to the first pixel. The first pixel may include an organic light-emitting diode that emits the light in response to the image data, memory to digitally store the image data received from the controller, and driver circuitry to receive the image data from the memory. The driver circuitry may cause the organic light-emitting diode to emit the light in response to the image data.

Memory-in-pixel architecture

An electronic display may include a memory formed in an active area of the electronic display or formed in integrated circuitry of the electronic display that is outside of the active area. The memory may store a digital data signal indicative of a value within a data range. The electronic display may include a driver disposed in the active area, where the driver may generate one or more analog electrical signals in response to the digital data signal. The electronic display may also include a light-modulating device disposed on the active area, where the light-modulating device may emit light based at least in part on the one or more analog electrical signals.

Systems and methods for memory circuitry in an electronic display

Systems, methods, and other embodiments associated with improving a static noise margin of memory cells by using charge sharing to under-drive a wordline are described. In one embodiment, a system includes power logic to, in response to a memory request, connect a voltage source with a virtual power network to store an electric charge within the virtual power network based on a voltage from the voltage source. The virtual power network includes a network of interconnects that electrically connect a plurality of driver interconnects. The system includes wordline logic to under-drive a requested wordline of a plurality of wordlines by connecting the requested wordline with the virtual power network to share the electric charge stored in the virtual power network with the requested wordline. The wordline logic under-drives a voltage of the requested wordline to be lower than a source voltage provided by the voltage source.

Wordline under-driving using a virtual power network

Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

Tunneling field-effect transistor with direct tunneling for enhanced tunneling current

Apparatuses, systems, and methods for tunneling MOSFETs (TFETs) using a self-aligned heterostructure source and isolated drain. TFETs that have an abrupt junction between source and drain regions have an increased probability of carrier direct tunneling (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction.

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Albany, CA, United States of America

Kanghoon Jeon