Samsung Electronics Co., Ltd.

Konkuk University Industrial Cooperation Corp

Sungkyunkwan University

Electronics and Telecommunications Research Institute

Gct Semiconductor, Inc.

Kang-yoon Lee

Bong-Soo Kim

Jae-Man Yoon

Hyeoung-won Seo

Seong-goo Kim

Dong-Gun Park

Seung-bae Park

Jong-woo Park

Jae-Sup Lee

Sang-yun Kim

Joon-Sung Park

Sang-ho Kim

Tae-Wook Kim

Choong-yul Cha

Hyung-sun Lee

Gwan-hyung Kim

Young-Woong Son

Sung-hun Cho

Young-Gun Pu

An-Soo Park

Ho-chul Ryu

Choong-Ho Lee

Sang-Wook Kwon

Sung-Bum Park

Kyeongho Lee

Sung-Ku Yeo

Dong-Soo Lee

Jeong Woo Lee

Joonbae Park

Yun-Gi Kim

Sangsung Choi

Cheol-Ho Shin

Young-Ho Ryu

Jae-Seok Park

Young Ae Jeon

Mi Kyung Oh

Byoung Hak Kim

Eunseok Song

Seung Sik Lee

Dong-In Kim

Chang-Suk Hyun

Hyuck-Jin Kang

Sangjae Lee

Jae-sup Lee

Hamed Abbasizadeh

Thi Kim Nga Truong

YoungGun Pu

Seung Il Huh

Hyeong-Won Seo

Il-Young Moon

Kwang-bo Sim

Sang-Kil Jeon

An input device is provided. The input device includes a communicator for communicating with an electronic device, a pen tip provided on one end portion of the input device, an electrode part provided at a position spaced apart at a predetermined interval from the pen tip, and a processor configured to apply a predetermined frequency signal to the electrode part, and control the communicator so as to transmit, to the electronic device, the signal of which frequency changed according to a capacitance formed between the electrode part and the electronic device.

Input device including pen tip, electronic system and control method therefor

Disclosed is an input device. The input device includes a communicator configured to communicate with an electronic device, a pen tip provided at one end of the input device, a first electrode portion including a plurality of first sub-electrodes spaced apart from each other by a predetermined distance from the pen tip, a second electrode portion including a plurality of second sub-electrodes spaced apart from each other to correspond to each of the plurality of first sub-electrodes at a position spaced apart from the first electrode portion by a predetermined distance, a processor to provide a driving signal to the first electrode portion and the second electrode portion, generate tilt information of the input device on the basis of a plurality of capacitances formed between the plurality of first sub-electrodes and the plurality of second sub-electrodes, and transmit the tilt information to the electronic device.

Input device, electronic system and control method therefor

An electronic device is provided. The electronic device includes a receiving circuit configured to wirelessly receive power and output AC power, a rectifying circuit configured to rectify the AC power from the receiving circuit, wherein the rectifying circuit may include a first P-MOSFET configured to transfer a positive amplitude of power to an output terminal of the rectifying circuit while the AC power has the positive amplitude and to prevent transferring a negative amplitude of power to the output terminal of the rectifying circuit while the AC power has the negative amplitude, and a forward loss compensating circuit connected with the first P-MOSFET configured to reduce a threshold voltage of the first P-MOSFET while the AC power has the positive amplitude.

Electronic device for wirelessly receiving power and method for operating the same

A digital Phase Locked Loop (PLL) in a wireless communication system is provided. The PLL includes a Digitally Controlled Oscillator (DCO), a divider, a Phase Frequency Detector (PFD), a Time to Digital Converter (TDC), a delay comparator, and a level scaler. The DCO generates a frequency signal depending on an input Digital Tuning Word (DTW). The divider divides the frequency signal at an integer ratio. The PFD generates a signal representing a phase difference between a divided frequency signal and a reference signal. The TDC measures a time interval of the phase difference using the signal representing the phase difference. The delay comparator calculates a time interval in the case where rising edges coincide from values measured by the TDC. The level scaler generates a DTW that operates the DCO using a digital code representing the time interval.

Digital phase locked loop device and method in wireless communication system

A digital phase-locked loop apparatus using FSK includes a PFD detecting phase differences between a reference clock and a frequency-divided signal, and a first adder for generating first digital control codes by adding first digital codes, second digital codes, and channel frequency codes including channel information to each other, the first digital codes being converted from time differences between first and second pulses. The apparatus further includes a digital filter correcting errors of the first digital control codes to generate second digital control codes, a DCO for varying an oscillating frequency in accordance with a digital tuning word based on the second digital control codes, and a dual modulus division unit dividing the oscillating frequency into a frequency-divided signal.

Digital phase-locked loop apparatus using frequency shift keying and method of controlling the same

Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4Fstructure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.

Semiconductor memory device having vertical channel transistor and method for fabricating the same

A Time-to-Digital Converter (TDC) is provided. The TDC includes a first TDC unit for receiving a first input signal and a second input signal, delaying the first input signal on a specific time basis using each of first delay blocks, generating first phase-divided signals by performing first phase division on signals of input/output nodes for each of the first delay blocks on a predefined Phase-Interpolation (PI) delay time basis, and outputting the second input signal and a phase-divided signal closest to the second input signal, among the first phase-divided signals, a time amplifier for independently time-amplifying the second input signal and the phase-divided signal closest to the second input signal, and a second TDC unit for delaying a phase-divided signal closest to the time-amplified second input signal on a specific time basis using each of second delay blocks, and generating second phase-divided signals by performing second phase division on signals of input/output nodes for each of the second delay blocks on a predefined PI delay time basis.

Time-to-digital converter and operation method thereof

A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.

Method of fabricating semiconductor device with cell epitaxial layers partially overlap buried cell gate electrode

In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar. A second doped region is formed on the body portion of the pillar and connected electrically to the bitline. Storage node electrodes are connected electrically to the first doped region and disposed on each of the pillar portions.

Semiconductor memory device with vertical channel formed on semiconductor pillars

A digitally controlled oscillator (DCO) includes a current generator which generates an electric current having a magnitude corresponding to an input signal, and a digitally controlled oscillating unit which generates an oscillating frequency based on an inductance which varies according to the magnitude of the electric current generated by the current generator.

Digitally controlled oscillator (DCO)

There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

Semiconductor device having vertical transistor and method of fabricating the same

A semiconductor device having a vertical channel capable of reducing the interface contact resistance between a gate electrode surrounding an active pillar and a word line connecting the gate electrode and a method of manufacturing the same is provided. The semiconductor device includes a plurality of active pillars extending in a direction perpendicular to a surface of a semiconductor substrate. A word line structure is formed on an outer periphery for connecting the active pillars disposed in the same row or column. Top and bottom source/drain regions are formed over and under the active pillars, respectively, in relation to the word line structure.

Semiconductor device having a vertical channel and method of manufacturing same

DRAM device with cell epitaxial layers partially overlap buried cell gate electrode

Growing community of inventors

Seongnam-si, South Korea

Kang-yoon Lee