Samsung Electronics Co., Ltd.

Kang-Yoon Lee

Dong-Gun Park

Bong-Soo Kim

Jae-Man Yoon

Hyeoung-won Seo

Cheol-Ju Yun

Seong-goo Kim

Jong-woo Park

Yoo-Cheol Shin

Jeong-Seok Kim

Woo-Tag Kang

In-Ho Nam

A method of forming a semiconductor device including a memory cell area having a plurality of memory cells and a peripheral circuit area for reading and writing data on the memory cells in the memory cell area of a semiconductor substrate is provided. Contact pads are formed on source/drain regions of transistors in the peripheral circuit area as well as in the memory cell area. The contact pads are concurrently formed on the source/drain regions of the transistors in the memory cell area and the peripheral circuit area. As a result, there is no step difference between the contact pads and, thus, it is easy to form metal contact plugs on the contact pads.

Method of forming semiconductor device having contact pad on source/drain region in peripheral circuit area

There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.

Semiconductor device having vertical transistor and method of fabricating the same

Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.

Semiconductor device having storage nodes and its method of fabrication

An integrated circuit device includes a substrate that has a trench formed therein. An isolation layer is disposed in the trench and covers a first sidewall portion of the trench. A gate electrode is disposed on a second sidewall portion of the trench.

Integrated circuit devices having active regions with expanded effective widths and methods of manufacturing same

Methods of forming integrated circuit memory devices may include steps to form memory cell access transistors therein. These steps may include steps to form a gate line on a semiconductor substrate and then implant dopants of first conductivity type into the semiconductor substrate to define a self-aligned impurity region therein. A spacer layer of a first material is then formed on a sidewall and upper surface of the gate line. An interlayer insulating layer of a second material is then formed on the spacer layer. A series of selective etching steps are then performed using different etchants. For example, a step is performed to selectively etch the interlayer insulating layer to define a contact hole therein, using the spacer layer as an etching mask to protect the gate line from etching damage. A selective etching step is then performed to convert the spacer layer into a sidewall spacer on the sidewall of the gate line. This etching step is performed using the interlayer insulating layer as an etching mask. A conductive plug (e.g., bit line plug) is then formed in the contact hole. This conductive plug forms an ohmic contact with the impurity region.

Methods of forming integrated circuit memory devices using masking layers to inhibit overetching of impurity regions and conductive lines

A dynamic random access memory (DRAM) cell storage node and a fabricating method thereof are provided. A storage contact plug,is formed in a first insulating layer,on a semiconductor substrate. A second insulating layer,a material layer,and a third insulating layer,are sequentially formed on the first insulating layer. The material layer prevents etchant of the third insulating layer from attacking the second insulating layer. The third insulating layer, the material layer, and the second insulating layer are sequentially etched to form an opening exposing the storage contact plug and a portion of the surface of the first insulating layer. The opening is filled with a conductive layer to form a storage node,The third insulating layer is etched until the top surface of the material layer is exposed, and the material layer is etched until the top surface of the second insulating layer is exposed. Overetching is thus prevented, avoiding collapse or breakage of the storage node, dielectric leakage, and defective step coverage of upper electrodes.

Method for fabricating a DRAM cell storage node

Methods of forming field effect transistors include the steps of forming an insulated gate electrode on a face of a substrate containing a semiconductor region therein extending to the face. A conductive layer of first conductivity type is also formed on the face and on a sidewall and upper surface of the insulated gate electrode. Dopants of first conductivity type are then diffused from the conductive layer into the semiconductor region to define source and drain regions of first conductivity type therein which are self-aligned to the insulated gate electrode. A step is also performed to remove a portion of the conductive layer to thereby define an intermediate source/drain contact (which is also self-aligned to the insulated gate electrode) and expose the upper surface of the insulated gate electrode. An electrode is then formed in contact with the intermediate source/drain contact.

Methods of forming field effect transistors having self-aligned

A trench is formed in a substrate, the trench defining an active region surface on the substrate, the trench having a trench sidewall. A trench insulation region is then formed in the trench. The substrate underlying the trench sidewall is doped with impurities, and after the first doping, the substrate underlying the active region surface is doped with impurities to form a well having an impurity concentration which increases towards the trench sidewall in a predetermined manner. To form the trench, an insulation layer preferably is formed on the substrate, a barrier layer is formed on the insulation layer, and the barrier layer and the insulation layer are patterned to form an insulation region on the substrate and a barrier region on the insulation region. The substrate is then etched using the barrier region and the insulation region as a mask to thereby form a trench in the substrate. Preferably, the first doping includes implanting ions into the substrate through the trench insulation region and the trench sidewall using the barrier region as a mask. The second doping preferably is preceded by removal of the barrier region, and includes implanting ions into the substrate through the active region surface. The first implantation preferably occurs at a predetermined angle of incidence oblique to the active region surface or, more preferably, over a predetermined range of angles of incidence. The first and second doping steps may include doping with impurities of the same conductivity type or with opposite conductivity types.

Growing community of inventors

Kyungki-do, South Korea

Kang-Yoon Lee