Micron Technology Incorporated

Nan Ya Technology Corporation

Kang-Yong Kim

Hyun Yoo Lee

Yang Lu

Hyunyoo Lee

Dean D Gans

John David Porter

Taeksang Song

Saira Samar Malik

John Christopher Sancon

Keun Soo Song

Huy Thanh Vo

Mark K Hadrick

Jacob Robert Anderson

Timothy Mowry Hollis

Chinnakrishnan Ballapuram

Sourabh Dhir

Dong Soon Lim

Zer Liang

Tadashi Yamamoto

Francesco Douglas Verna-Ketel

Yu-Sheng Hsu

Creston M Dupree

Smruti Subhash Jhaveri

Jeffrey P Wright

George B Raad

Atsushi Hatakeyama

Jongtae Kwak

Venkatraghavan Bringivijayaraghavan

Eric J Stave

Nathaniel J Meier

Chulmin Jung

Vijayakrishna J Vankayala

Erik T Barmon

Ke Wei Chan

Akiyoshi Yamamoto

Jason McBride Brown

This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.

Memory die interconnections to physical layer interfaces

Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Apparatuses and methods including multilevel command and address signals

Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include a controller with logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

Bank-level self-refresh

Methods, systems, and devices for die voltage regulation are described. A device may include a first die and second die. A component that generates voltage on the first die may be connected to a capacitor on the second die through a conductive line. The conductive line may allow the capacitor on the second die to regulate voltage generated by the component on the first die.

Voltage generation and regulation across multiple dies

This document describes apparatuses and techniques for die-based rank management for a memory system. In various aspects, a die-based rank controller (controller) can determine which memory dies of a memory device are not functional to store data and correlate rank selections of a memory system to ranks of other memory dies (e.g., functional memory dies). The controller may store information that indicates the correlation or mapping of the rank selections to the ranks of the other memory dies to enable access to those ranks of the memory system. In some aspects, the controller receives a command to access the memory device with a rank selection, and the controller enables access to a corresponding rank based on the information. By so doing, aspects of die-based rank management enable memory packages with non-functional memory dies to be used instead of discarded, which can increase production utilization or lower manufacturing costs.

Die-based rank management

Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

Automated error correction with memory refresh

Described apparatuses and methods relate to adaptive wordline refresh for a memory system that may support a nondeterministic protocol. To help manage power delivery networks in a memory system, a memory device can include logic that can stagger activation of multiple wordlines that are to be activated or refreshed approximately simultaneously. The logic circuitry can be coupled between wordlines that are to be activated and delay propagation of the activation signal. Thus, a first group of wordlines (e.g., 'before' the logic circuitry) are activated by the signal, but activation of a second group of wordlines (e.g., “after” the logic circuitry), is delayed, reducing the peak current draw. Additional logic circuitries can be coupled between the wordlines to divide the wordlines into multiple groups, thereby staggering the activation of wordlines that are activated by a refresh command, which can reduce the peak current draw and power consumption.

Adaptive wordline refresh

Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.

Dynamic address scramble

This document describes apparatuses and techniques for write timing compensation. In various aspects, a write timing compensator of a memory controller can apply a delay to data signals transmitted to a memory circuit based on various operating parameters, which may include voltage or latency information. In some cases, the memory controller or memory circuit powers components of write timing compensation circuitry using a dynamic power rail that scales with an operating voltage of the memory circuit. By so doing, the write timing compensator or compensation circuits may improve signal integrity of data signals communicated between the memory controller and the memory circuit at different frequencies and voltages.

Write timing compensation

Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The 'asymmetric' term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.

Asymmetric read-write sequence for interconnected dies

In various examples, refreshing a bank can include receiving a refresh command, wherein the refresh command comprises selector bits and receiving mode register bits from the mode registers. Refreshing a bank can also include refreshing a number of banks from the plurality of banks utilizing the mode register bits and the selector bits.

Bank selection for refreshing

Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

Described apparatuses and methods relate to selectively disabling a die that may be included in a multiple-die package without necessarily disabling all the remaining dies within the package. A nonvolatile circuit, such as one or more fuses, may be included within individual dies and/or otherwise incorporated within the package. The nonvolatile circuit maintains a value for the die that is indicative of the operability of the die. Die disablement logic is operatively coupled to the nonvolatile circuit and can disable the die based on the value indicating that the die is unusable. The disabling of the die by the die disablement logic may be controlled by an override signal that allows the disabling or prevents the logic from disabling the die. Thus, the die disablement logic can prevent a defective die from functioning, but the die disablement logic may be overridden for testing or debugging.

Die disablement

An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Memory channel disablement

Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice over a bus to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, the controller may attempt to train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine the bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

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Boise, ID, United States of America

Kang-Yong Kim